Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.48	98.75	96.74	100.00	92.31	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	860483	0	0
entropy_period_rd_A	2147483647	2792	0	0
intr_enable_rd_A	2147483647	3752	0	0
prefix_0_rd_A	2147483647	3263	0	0
prefix_10_rd_A	2147483647	3067	0	0
prefix_1_rd_A	2147483647	3199	0	0
prefix_2_rd_A	2147483647	3223	0	0
prefix_3_rd_A	2147483647	3080	0	0
prefix_4_rd_A	2147483647	3080	0	0
prefix_5_rd_A	2147483647	3075	0	0
prefix_6_rd_A	2147483647	2995	0	0
prefix_7_rd_A	2147483647	3226	0	0
prefix_8_rd_A	2147483647	3158	0	0
prefix_9_rd_A	2147483647	3120	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	860483	0	0
T8	645091	10045	0	0
T16	793617	56811	0	0
T23	0	67214	0	0
T29	0	120674	0	0
T35	286823	37589	0	0
T36	522527	0	0	0
T37	243772	0	0	0
T79	0	108182	0	0
T97	1174	0	0	0
T120	0	47871	0	0
T121	0	21522	0	0
T122	0	106384	0	0
T123	0	65857	0	0
T124	332461	0	0	0
T125	666349	0	0	0
T126	127487	0	0	0
T127	99682	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2792	0	0
T9	256768	0	0	0
T16	793617	127	0	0
T86	0	28	0	0
T97	1174	0	0	0
T125	666349	0	0	0
T126	127487	0	0	0
T127	99682	0	0	0
T128	47021	0	0	0
T135	105892	0	0	0
T140	0	73	0	0
T141	0	19	0	0
T142	0	23	0	0
T143	0	203	0	0
T144	0	457	0	0
T145	0	44	0	0
T146	0	54	0	0
T147	0	7	0	0
T148	55158	0	0	0
T149	19518	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3752	0	0
T9	256768	0	0	0
T16	793617	169	0	0
T86	0	21	0	0
T97	1174	0	0	0
T125	666349	0	0	0
T126	127487	0	0	0
T127	99682	0	0	0
T128	47021	0	0	0
T135	105892	0	0	0
T140	0	72	0	0
T141	0	27	0	0
T142	0	31	0	0
T143	0	450	0	0
T144	0	463	0	0
T145	0	14	0	0
T146	0	55	0	0
T147	0	49	0	0
T148	55158	0	0	0
T149	19518	0	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3263	0	0
T9	256768	0	0	0
T16	793617	154	0	0
T86	0	32	0	0
T97	1174	0	0	0
T125	666349	0	0	0
T126	127487	0	0	0
T127	99682	0	0	0
T128	47021	0	0	0
T135	105892	0	0	0
T140	0	45	0	0
T141	0	10	0	0
T142	0	7	0	0
T143	0	450	0	0
T144	0	421	0	0
T145	0	74	0	0
T146	0	11	0	0
T147	0	35	0	0
T148	55158	0	0	0
T149	19518	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3067	0	0
T9	256768	0	0	0
T16	793617	123	0	0
T86	0	15	0	0
T97	1174	0	0	0
T125	666349	0	0	0
T126	127487	0	0	0
T127	99682	0	0	0
T128	47021	0	0	0
T135	105892	0	0	0
T140	0	86	0	0
T141	0	14	0	0
T142	0	12	0	0
T143	0	495	0	0
T144	0	456	0	0
T145	0	60	0	0
T146	0	16	0	0
T147	0	33	0	0
T148	55158	0	0	0
T149	19518	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3199	0	0
T9	256768	0	0	0
T16	793617	189	0	0
T86	0	27	0	0
T97	1174	0	0	0
T125	666349	0	0	0
T126	127487	0	0	0
T127	99682	0	0	0
T128	47021	0	0	0
T135	105892	0	0	0
T140	0	83	0	0
T141	0	10	0	0
T142	0	16	0	0
T143	0	460	0	0
T144	0	447	0	0
T145	0	37	0	0
T146	0	27	0	0
T147	0	32	0	0
T148	55158	0	0	0
T149	19518	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3223	0	0
T9	256768	0	0	0
T16	793617	177	0	0
T86	0	6	0	0
T97	1174	0	0	0
T125	666349	0	0	0
T126	127487	0	0	0
T127	99682	0	0	0
T128	47021	0	0	0
T135	105892	0	0	0
T140	0	81	0	0
T141	0	2	0	0
T142	0	25	0	0
T143	0	503	0	0
T144	0	456	0	0
T145	0	26	0	0
T146	0	33	0	0
T147	0	18	0	0
T148	55158	0	0	0
T149	19518	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3080	0	0
T9	256768	0	0	0
T16	793617	117	0	0
T86	0	12	0	0
T97	1174	0	0	0
T125	666349	0	0	0
T126	127487	0	0	0
T127	99682	0	0	0
T128	47021	0	0	0
T135	105892	0	0	0
T140	0	44	0	0
T141	0	11	0	0
T142	0	10	0	0
T143	0	441	0	0
T144	0	443	0	0
T145	0	68	0	0
T146	0	21	0	0
T147	0	14	0	0
T148	55158	0	0	0
T149	19518	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3080	0	0
T9	256768	0	0	0
T16	793617	119	0	0
T86	0	17	0	0
T97	1174	0	0	0
T125	666349	0	0	0
T126	127487	0	0	0
T127	99682	0	0	0
T128	47021	0	0	0
T135	105892	0	0	0
T140	0	75	0	0
T141	0	13	0	0
T142	0	22	0	0
T143	0	443	0	0
T144	0	476	0	0
T145	0	43	0	0
T146	0	41	0	0
T147	0	18	0	0
T148	55158	0	0	0
T149	19518	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3075	0	0
T9	256768	0	0	0
T16	793617	140	0	0
T86	0	23	0	0
T97	1174	0	0	0
T125	666349	0	0	0
T126	127487	0	0	0
T127	99682	0	0	0
T128	47021	0	0	0
T135	105892	0	0	0
T140	0	55	0	0
T141	0	12	0	0
T142	0	26	0	0
T143	0	509	0	0
T144	0	443	0	0
T145	0	84	0	0
T146	0	25	0	0
T147	0	13	0	0
T148	55158	0	0	0
T149	19518	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2995	0	0
T9	256768	0	0	0
T16	793617	185	0	0
T86	0	23	0	0
T97	1174	0	0	0
T125	666349	0	0	0
T126	127487	0	0	0
T127	99682	0	0	0
T128	47021	0	0	0
T135	105892	0	0	0
T140	0	57	0	0
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T147	0	3	0	0
T148	55158	0	0	0
T149	19518	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3226	0	0
T9	256768	0	0	0
T16	793617	179	0	0
T86	0	35	0	0
T97	1174	0	0	0
T125	666349	0	0	0
T126	127487	0	0	0
T127	99682	0	0	0
T128	47021	0	0	0
T135	105892	0	0	0
T140	0	79	0	0
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T142	0	14	0	0
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T144	0	459	0	0
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T146	0	17	0	0
T147	0	22	0	0
T148	55158	0	0	0
T149	19518	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3158	0	0
T9	256768	0	0	0
T16	793617	175	0	0
T86	0	15	0	0
T97	1174	0	0	0
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T127	99682	0	0	0
T128	47021	0	0	0
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T140	0	26	0	0
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T147	0	36	0	0
T148	55158	0	0	0
T149	19518	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3120	0	0
T9	256768	0	0	0
T16	793617	188	0	0
T86	0	18	0	0
T97	1174	0	0	0
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T127	99682	0	0	0
T128	47021	0	0	0
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T150	0	4	0	0