Unified Coverage Report :: Module :: kmac_staterd

Module : kmac_staterd

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.00	100.00	70.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_staterd.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_staterd	90.00	100.00	70.00			100.00

---

Module Instance : tb.dut.u_staterd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.00	100.00	70.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	89.72	80.74			88.30	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.48	98.75	96.74	100.00	92.31	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_slicer[0].u_state_slice	100.00	100.00					100.00
gen_slicer[1].u_state_slice	100.00	100.00					100.00
u_tlul_adapter	89.44	89.12	81.15			87.50	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : kmac_staterd

	Line No.	Total	Covered	Percent
TOTAL		10	10	100.00
ALWAYS	82	4	4	100.00
CONT_ASSIGN	90	1	1	100.00
ALWAYS	96	3	3	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	118	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_staterd.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_staterd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
82	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
90	1	1
96	2	2
97	1	1
116	1	1
118	1	1

---

Cond Coverage for Module : kmac_staterd

	Total	Covered	Percent
Conditions	10	7	70.00
Logical	10	7	70.00
Non-Logical	0	0
Event	0	0

 LINE       84
 EXPRESSION (tlram_req & ((~tlram_we)))
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (tlram_req & ((~tlram_we)))
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       97
 EXPRESSION (tlram_req & ((!tlram_we)))
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       118
 EXPRESSION ((int'(addr_sel) < Share) ? muxed_state[addr_sel] : 0)
             ------------1-----------

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

---

Branch Coverage for Module : kmac_staterd

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	118	1	1	100.00
IF	82	3	3	100.00
IF	96	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_staterd.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_staterd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	118	((int'(addr_sel) < Share)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	82	if ((!rst_ni))
-2-:	84	if ((tlram_req & (~tlram_we)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3