Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	257097425	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

184547808

1

T1

70889

T2

927358

T3

96

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	228379926	1			T1	78971		T2	118220		T3	41
values[0x0]	102487914	1			T1	18602		T2	556592		T3	54
values[0x1]	110777393	1			T1	19530		T2	605435		T3	52

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	199833628	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

241811605

1

T1

81752

T2

123985

T3

113

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2272150	1			T1	435		T2	9138		T3	1
valid_sources[0x01]	1349914	1			T1	470		T2	9171		T3	1
valid_sources[0x02]	1322372	1			T1	440		T2	9237		T3	1
valid_sources[0x03]	2172425	1			T1	419		T2	9232		T4	1809
valid_sources[0x04]	4299386	1			T1	472		T2	9416		T3	1
valid_sources[0x05]	1981427	1			T1	477		T2	9128		T4	1812
valid_sources[0x06]	1321600	1			T1	437		T2	9040		T4	1574
valid_sources[0x07]	1336224	1			T1	449		T2	9300		T3	1
valid_sources[0x08]	1532388	1			T1	419		T2	9193		T4	1814
valid_sources[0x09]	1321001	1			T1	501		T2	9127		T4	1672
valid_sources[0x0a]	2176615	1			T1	437		T2	9156		T3	1
valid_sources[0x0b]	1323664	1			T1	464		T2	9154		T3	1
valid_sources[0x0c]	1773096	1			T1	475		T2	9146		T3	1
valid_sources[0x0d]	3654505	1			T1	439		T2	9135		T4	1728
valid_sources[0x0e]	1322551	1			T1	483		T2	9191		T3	2
valid_sources[0x0f]	1316694	1			T1	474		T2	9287		T4	1660
valid_sources[0x10]	2836881	1			T1	483		T2	9201		T3	1
valid_sources[0x11]	1323582	1			T1	483		T2	9227		T4	1781
valid_sources[0x12]	1327324	1			T1	425		T2	9161		T3	1
valid_sources[0x13]	2666136	1			T1	427		T2	9352		T4	1703
valid_sources[0x14]	1461597	1			T1	460		T2	9270		T4	1670
valid_sources[0x15]	1362384	1			T1	428		T2	9220		T4	1726
valid_sources[0x16]	1760440	1			T1	477		T2	9103		T3	1
valid_sources[0x17]	1319159	1			T1	491		T2	9173		T4	1670
valid_sources[0x18]	3655726	1			T1	482		T2	9170		T3	1
valid_sources[0x19]	1331743	1			T1	482		T2	9208		T4	1717
valid_sources[0x1a]	2196819	1			T1	434		T2	9200		T4	1688
valid_sources[0x1b]	1320537	1			T1	455		T2	9016		T4	1791
valid_sources[0x1c]	1321744	1			T1	481		T2	9023		T4	1809
valid_sources[0x1d]	1321671	1			T1	431		T2	9136		T4	1574
valid_sources[0x1e]	1319327	1			T1	416		T2	9117		T3	1
valid_sources[0x1f]	1318347	1			T1	481		T2	9170		T4	1620
valid_sources[0x20]	1315563	1			T1	502		T2	9224		T3	1
valid_sources[0x21]	1340977	1			T1	506		T2	9040		T4	1805
valid_sources[0x22]	3638658	1			T1	432		T2	9098		T4	1712
valid_sources[0x23]	2184045	1			T1	432		T2	9007		T3	1
valid_sources[0x24]	1321877	1			T1	458		T2	9153		T4	1716
valid_sources[0x25]	1325001	1			T1	468		T2	9270		T4	1759
valid_sources[0x26]	1349442	1			T1	492		T2	9089		T4	1808
valid_sources[0x27]	4579062	1			T1	449		T2	9113		T4	1705
valid_sources[0x28]	1410868	1			T1	472		T2	9121		T4	1807
valid_sources[0x29]	2928210	1			T1	425		T2	9005		T3	3
valid_sources[0x2a]	1319053	1			T1	442		T2	9241		T3	1
valid_sources[0x2b]	1322518	1			T1	447		T2	9159		T4	1721
valid_sources[0x2c]	1418047	1			T1	492		T2	9138		T4	1685
valid_sources[0x2d]	1317393	1			T1	448		T2	9268		T4	1757
valid_sources[0x2e]	1371607	1			T1	464		T2	9116		T4	1832
valid_sources[0x2f]	3627803	1			T1	422		T2	8990		T3	1
valid_sources[0x30]	1328027	1			T1	490		T2	9142		T3	1
valid_sources[0x31]	1321815	1			T1	431		T2	9139		T4	1819
valid_sources[0x32]	1315207	1			T1	445		T2	9035		T4	1801
valid_sources[0x33]	1350387	1			T1	504		T2	9168		T4	1686
valid_sources[0x34]	3399066	1			T1	476		T2	9304		T4	1805
valid_sources[0x35]	1783224	1			T1	452		T2	9271		T3	3
valid_sources[0x36]	1323268	1			T1	488		T2	9001		T4	1688
valid_sources[0x37]	1962868	1			T1	455		T2	9190		T3	2
valid_sources[0x38]	1320612	1			T1	425		T2	9255		T4	1811
valid_sources[0x39]	1318011	1			T1	456		T2	9137		T3	2
valid_sources[0x3a]	1323157	1			T1	484		T2	9057		T4	1671
valid_sources[0x3b]	1326132	1			T1	490		T2	9246		T4	1754
valid_sources[0x3c]	1986537	1			T1	473		T2	9186		T4	1727
valid_sources[0x3d]	1325625	1			T1	433		T2	9178		T4	1863
valid_sources[0x3e]	1324359	1			T1	480		T2	9062		T3	1
valid_sources[0x3f]	1316480	1			T1	490		T2	9221		T3	2
valid_sources[0x40]	1324458	1			T1	466		T2	9197		T4	1798
valid_sources[0x41]	1353739	1			T1	446		T2	9252		T3	2
valid_sources[0x42]	1610685	1			T1	473		T2	9160		T4	1663
valid_sources[0x43]	1320828	1			T1	469		T2	9282		T3	2
valid_sources[0x44]	3296207	1			T1	432		T2	9227		T4	1659
valid_sources[0x45]	2202314	1			T1	430		T2	9068		T3	1
valid_sources[0x46]	1352392	1			T1	456		T2	9206		T4	1762
valid_sources[0x47]	1319109	1			T1	415		T2	8882		T4	1737
valid_sources[0x48]	1327569	1			T1	485		T2	9218		T3	3
valid_sources[0x49]	1318749	1			T1	456		T2	9141		T4	1737
valid_sources[0x4a]	2031986	1			T1	419		T2	9101		T4	1807
valid_sources[0x4b]	3931858	1			T1	425		T2	9079		T4	1691
valid_sources[0x4c]	1324724	1			T1	449		T2	9277		T3	2
valid_sources[0x4d]	1458126	1			T1	466		T2	9104		T4	1821
valid_sources[0x4e]	1347555	1			T1	422		T2	9276		T3	1
valid_sources[0x4f]	1325599	1			T1	462		T2	9107		T4	1679
valid_sources[0x50]	1319991	1			T1	466		T2	9105		T4	1753
valid_sources[0x51]	1321768	1			T1	412		T2	9116		T4	1773
valid_sources[0x52]	1428821	1			T1	503		T2	9001		T4	1734
valid_sources[0x53]	1326608	1			T1	489		T2	9251		T4	1646
valid_sources[0x54]	1474596	1			T1	450		T2	9261		T4	1668
valid_sources[0x55]	1533729	1			T1	434		T2	9135		T3	1
valid_sources[0x56]	1347632	1			T1	432		T2	9094		T4	1790
valid_sources[0x57]	1325701	1			T1	476		T2	9211		T4	1797
valid_sources[0x58]	1327050	1			T1	506		T2	9238		T4	1818
valid_sources[0x59]	1381777	1			T1	429		T2	9177		T4	1728
valid_sources[0x5a]	1368279	1			T1	447		T2	9014		T3	1
valid_sources[0x5b]	2169156	1			T1	420		T2	9242		T3	1
valid_sources[0x5c]	2183894	1			T1	498		T2	9197		T4	1686
valid_sources[0x5d]	1434092	1			T1	486		T2	9026		T3	1
valid_sources[0x5e]	6028735	1			T1	465		T2	9094		T4	1790
valid_sources[0x5f]	1319540	1			T1	452		T2	9162		T4	1673
valid_sources[0x60]	1320629	1			T1	472		T2	9078		T4	1806
valid_sources[0x61]	1323100	1			T1	427		T2	8909		T4	1723
valid_sources[0x62]	6454635	1			T1	447		T2	9040		T4	1752
valid_sources[0x63]	1407753	1			T1	435		T2	9127		T3	2
valid_sources[0x64]	1324239	1			T1	431		T2	9076		T3	2
valid_sources[0x65]	1332646	1			T1	509		T2	9202		T4	1754
valid_sources[0x66]	1343186	1			T1	501		T2	9062		T3	1
valid_sources[0x67]	1978529	1			T1	483		T2	9242		T4	1773
valid_sources[0x68]	3793864	1			T1	480		T2	9257		T4	1848
valid_sources[0x69]	1328276	1			T1	488		T2	9147		T3	2
valid_sources[0x6a]	1325776	1			T1	451		T2	9164		T4	1728
valid_sources[0x6b]	4266580	1			T1	430		T2	9200		T4	1605
valid_sources[0x6c]	1319430	1			T1	453		T2	9072		T3	1
valid_sources[0x6d]	2185808	1			T1	460		T2	9099		T3	2
valid_sources[0x6e]	1880998	1			T1	454		T2	9165		T3	2
valid_sources[0x6f]	1394669	1			T1	444		T2	9224		T4	1726
valid_sources[0x70]	1327636	1			T1	435		T2	9086		T4	1711
valid_sources[0x71]	1321744	1			T1	473		T2	9256		T3	1
valid_sources[0x72]	1325790	1			T1	459		T2	9260		T4	1746
valid_sources[0x73]	2126115	1			T1	445		T2	9136		T3	3
valid_sources[0x74]	1343800	1			T1	518		T2	9093		T4	1759
valid_sources[0x75]	1319403	1			T1	454		T2	9183		T3	1
valid_sources[0x76]	1328292	1			T1	429		T2	9065		T4	1775
valid_sources[0x77]	1325232	1			T1	431		T2	9166		T3	4
valid_sources[0x78]	1324349	1			T1	431		T2	8980		T3	1
valid_sources[0x79]	1789352	1			T1	454		T2	9214		T3	2
valid_sources[0x7a]	2164092	1			T1	475		T2	9243		T3	1
valid_sources[0x7b]	1514231	1			T1	460		T2	9170		T3	1
valid_sources[0x7c]	1318646	1			T1	444		T2	9224		T3	1
valid_sources[0x7d]	1470259	1			T1	437		T2	9207		T4	1658
valid_sources[0x7e]	2235927	1			T1	429		T2	8992		T4	1699
valid_sources[0x7f]	1316316	1			T1	441		T2	9126		T3	2
valid_sources[0x80]	1324392	1			T1	405		T2	9264		T4	1736

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

71173858

1

T1

48938

T2

336527

T3

20

values[0x0]

all_enables

biggest_size

60870986

1

T1

11774

T2

319036

T3

43

values[0x1]

all_enables

biggest_size

52502964

1

T1

10177

T2

271795

T3

33