Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

259565346

1

T1

46214

T2

141687

T3

51

full_word

184702319

1

T1

70889

T2

927358

T3

96

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	444267335	1			T1	117103		T2	234423		T3	147
auto[TlIntgErrCmd]	125	1			T119	11		T120	7		T121	3
auto[TlIntgErrData]	95	1			T119	5		T120	7		T121	3
auto[TlIntgErrBoth]	110	1			T119	4		T120	6		T121	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

228857747

1

T1

78971

T2

118220

T3

41

auto[1]

215409918

1

T1

38132

T2

116202

T3

106

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	157645326	1			T1	30033		T2	845680		T3	21
auto[TlIntgErrNone]	partial	auto[1]	101919720	1			T1	16181		T2	571196		T3	30
auto[TlIntgErrNone]	full_word	auto[0]	71212287	1			T1	48938		T2	336527		T3	20
auto[TlIntgErrNone]	full_word	auto[1]	113490002	1			T1	21951		T2	590831		T3	76
auto[TlIntgErrCmd]	partial	auto[0]	51	1			T119	3		T120	2		T121	2
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T119	8		T120	4		T176	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T120	1		T121	1		T181	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T176	1		T182	1		T178	1
auto[TlIntgErrData]	partial	auto[0]	34	1			T119	1		T120	1		T121	2
auto[TlIntgErrData]	partial	auto[1]	53	1			T119	4		T120	4		T121	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T120	1		T182	1		T181	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T120	1		T180	1		T183	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T120	4		T121	1		T176	1
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T119	4		T120	2		T121	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T178	1		T184	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T121	1		T185	2		T181	1