Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	564500	0	0
entropy_period_rd_A	2147483647	1656	0	0
intr_enable_rd_A	2147483647	2483	0	0
prefix_0_rd_A	2147483647	1711	0	0
prefix_10_rd_A	2147483647	1625	0	0
prefix_1_rd_A	2147483647	1769	0	0
prefix_2_rd_A	2147483647	1795	0	0
prefix_3_rd_A	2147483647	1739	0	0
prefix_4_rd_A	2147483647	1872	0	0
prefix_5_rd_A	2147483647	1886	0	0
prefix_6_rd_A	2147483647	1635	0	0
prefix_7_rd_A	2147483647	1707	0	0
prefix_8_rd_A	2147483647	1790	0	0
prefix_9_rd_A	2147483647	1789	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	564500	0	0
T58	446877	63489	0	0
T59	610349	88987	0	0
T60	0	18627	0	0
T126	0	41562	0	0
T127	0	62242	0	0
T128	0	19335	0	0
T129	0	27249	0	0
T130	0	30750	0	0
T131	0	7559	0	0
T132	0	35242	0	0
T133	12482	0	0	0
T134	10820	0	0	0
T135	1734	0	0	0
T136	105453	0	0	0
T137	458143	0	0	0
T138	669864	0	0	0
T139	193694	0	0	0
T140	19996	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1656	0	0
T90	0	15	0	0
T99	0	7	0	0
T119	0	112	0	0
T125	0	12	0	0
T130	582335	79	0	0
T132	0	37	0	0
T148	0	73	0	0
T149	0	234	0	0
T150	0	5	0	0
T151	0	127	0	0
T152	47486	0	0	0
T153	1402	0	0	0
T154	161940	0	0	0
T155	797504	0	0	0
T156	506424	0	0	0
T157	190813	0	0	0
T158	430322	0	0	0
T159	49064	0	0	0
T160	258862	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2483	0	0
T90	0	15	0	0
T99	0	6	0	0
T119	0	144	0	0
T125	0	8	0	0
T130	582335	101	0	0
T132	0	33	0	0
T148	0	83	0	0
T149	0	225	0	0
T151	0	222	0	0
T152	47486	0	0	0
T153	1402	0	0	0
T154	161940	0	0	0
T155	797504	0	0	0
T156	506424	0	0	0
T157	190813	0	0	0
T158	430322	0	0	0
T159	49064	0	0	0
T160	258862	0	0	0
T161	0	13	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1711	0	0
T90	0	15	0	0
T99	0	3	0	0
T119	0	68	0	0
T125	0	2	0	0
T130	582335	83	0	0
T132	0	68	0	0
T148	0	97	0	0
T149	0	231	0	0
T151	0	195	0	0
T152	47486	0	0	0
T153	1402	0	0	0
T154	161940	0	0	0
T155	797504	0	0	0
T156	506424	0	0	0
T157	190813	0	0	0
T158	430322	0	0	0
T159	49064	0	0	0
T160	258862	0	0	0
T162	0	5	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1625	0	0
T90	0	19	0	0
T119	0	70	0	0
T125	0	5	0	0
T130	582335	51	0	0
T132	0	63	0	0
T148	0	40	0	0
T149	0	220	0	0
T151	0	201	0	0
T152	47486	0	0	0
T153	1402	0	0	0
T154	161940	0	0	0
T155	797504	0	0	0
T156	506424	0	0	0
T157	190813	0	0	0
T158	430322	0	0	0
T159	49064	0	0	0
T160	258862	0	0	0
T163	0	19	0	0
T164	0	3	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1769	0	0
T90	0	29	0	0
T119	0	68	0	0
T125	0	6	0	0
T130	582335	105	0	0
T132	0	56	0	0
T148	0	32	0	0
T149	0	220	0	0
T151	0	215	0	0
T152	47486	0	0	0
T153	1402	0	0	0
T154	161940	0	0	0
T155	797504	0	0	0
T156	506424	0	0	0
T157	190813	0	0	0
T158	430322	0	0	0
T159	49064	0	0	0
T160	258862	0	0	0
T163	0	19	0	0
T164	0	5	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1795	0	0
T90	0	21	0	0
T99	0	2	0	0
T119	0	85	0	0
T125	0	15	0	0
T130	582335	76	0	0
T132	0	65	0	0
T148	0	78	0	0
T149	0	232	0	0
T151	0	256	0	0
T152	47486	0	0	0
T153	1402	0	0	0
T154	161940	0	0	0
T155	797504	0	0	0
T156	506424	0	0	0
T157	190813	0	0	0
T158	430322	0	0	0
T159	49064	0	0	0
T160	258862	0	0	0
T163	0	13	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1739	0	0
T90	0	14	0	0
T99	0	10	0	0
T119	0	101	0	0
T125	0	5	0	0
T130	582335	73	0	0
T132	0	48	0	0
T148	0	63	0	0
T149	0	228	0	0
T151	0	202	0	0
T152	47486	0	0	0
T153	1402	0	0	0
T154	161940	0	0	0
T155	797504	0	0	0
T156	506424	0	0	0
T157	190813	0	0	0
T158	430322	0	0	0
T159	49064	0	0	0
T160	258862	0	0	0
T164	0	1	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1872	0	0
T90	0	17	0	0
T119	0	117	0	0
T125	0	6	0	0
T130	582335	85	0	0
T132	0	69	0	0
T148	0	42	0	0
T149	0	212	0	0
T151	0	219	0	0
T152	47486	0	0	0
T153	1402	0	0	0
T154	161940	0	0	0
T155	797504	0	0	0
T156	506424	0	0	0
T157	190813	0	0	0
T158	430322	0	0	0
T159	49064	0	0	0
T160	258862	0	0	0
T163	0	18	0	0
T165	0	23	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1886	0	0
T90	0	7	0	0
T99	0	2	0	0
T119	0	78	0	0
T125	0	13	0	0
T130	582335	91	0	0
T132	0	53	0	0
T148	0	60	0	0
T149	0	223	0	0
T151	0	251	0	0
T152	47486	0	0	0
T153	1402	0	0	0
T154	161940	0	0	0
T155	797504	0	0	0
T156	506424	0	0	0
T157	190813	0	0	0
T158	430322	0	0	0
T159	49064	0	0	0
T160	258862	0	0	0
T163	0	39	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1635	0	0
T90	0	13	0	0
T119	0	79	0	0
T125	0	8	0	0
T130	582335	42	0	0
T132	0	49	0	0
T148	0	71	0	0
T149	0	192	0	0
T151	0	232	0	0
T152	47486	0	0	0
T153	1402	0	0	0
T154	161940	0	0	0
T155	797504	0	0	0
T156	506424	0	0	0
T157	190813	0	0	0
T158	430322	0	0	0
T159	49064	0	0	0
T160	258862	0	0	0
T163	0	13	0	0
T164	0	1	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1707	0	0
T90	0	7	0	0
T119	0	79	0	0
T125	0	10	0	0
T130	582335	107	0	0
T132	0	37	0	0
T148	0	50	0	0
T149	0	199	0	0
T151	0	224	0	0
T152	47486	0	0	0
T153	1402	0	0	0
T154	161940	0	0	0
T155	797504	0	0	0
T156	506424	0	0	0
T157	190813	0	0	0
T158	430322	0	0	0
T159	49064	0	0	0
T160	258862	0	0	0
T163	0	6	0	0
T164	0	7	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1790	0	0
T90	0	18	0	0
T99	0	3	0	0
T119	0	73	0	0
T125	0	7	0	0
T130	582335	77	0	0
T132	0	40	0	0
T148	0	74	0	0
T149	0	226	0	0
T151	0	229	0	0
T152	47486	0	0	0
T153	1402	0	0	0
T154	161940	0	0	0
T155	797504	0	0	0
T156	506424	0	0	0
T157	190813	0	0	0
T158	430322	0	0	0
T159	49064	0	0	0
T160	258862	0	0	0
T163	0	14	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1789	0	0
T90	0	18	0	0
T99	0	5	0	0
T119	0	56	0	0
T125	0	4	0	0
T130	582335	81	0	0
T132	0	31	0	0
T148	0	70	0	0
T149	0	209	0	0
T151	0	240	0	0
T152	47486	0	0	0
T153	1402	0	0	0
T154	161940	0	0	0
T155	797504	0	0	0
T156	506424	0	0	0
T157	190813	0	0	0
T158	430322	0	0	0
T159	49064	0	0	0
T160	258862	0	0	0
T163	0	47	0	0