Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	260781168	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

187575137

1

T1

405075

T2

187

T3

212326

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	232105117	1			T1	511540		T2	90		T3	65977
values[0x0]	103905114	1			T1	224876		T2	52		T3	85662
values[0x1]	112346074	1			T1	241796		T2	56		T3	86247

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	202623272	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

245733033

1

T1

530368

T2

190

T3

219213

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1362839	1			T1	3777		T3	888		T4	7419
valid_sources[0x01]	1413130	1			T1	3945		T3	915		T4	7704
valid_sources[0x02]	1999484	1			T1	3648		T3	922		T4	7389
valid_sources[0x03]	2002993	1			T1	4079		T2	1		T3	891
valid_sources[0x04]	1361556	1			T1	3706		T3	895		T4	7442
valid_sources[0x05]	1359238	1			T1	3752		T2	2		T3	910
valid_sources[0x06]	1462088	1			T1	3749		T3	964		T4	7586
valid_sources[0x07]	2735982	1			T1	3832		T3	862		T4	7103
valid_sources[0x08]	1376471	1			T1	3792		T2	2		T3	924
valid_sources[0x09]	1383542	1			T1	3863		T3	933		T4	7746
valid_sources[0x0a]	1485652	1			T1	3670		T3	924		T4	7302
valid_sources[0x0b]	1360900	1			T1	3992		T2	2		T3	829
valid_sources[0x0c]	1524132	1			T1	3839		T3	932		T4	7335
valid_sources[0x0d]	1452666	1			T1	3947		T3	965		T4	7992
valid_sources[0x0e]	3696981	1			T1	3802		T2	1		T3	883
valid_sources[0x0f]	1354272	1			T1	3837		T3	1020		T4	7419
valid_sources[0x10]	1362799	1			T1	3750		T3	842		T4	7633
valid_sources[0x11]	1779090	1			T1	3992		T3	813		T4	6909
valid_sources[0x12]	1362079	1			T1	3874		T3	985		T4	7434
valid_sources[0x13]	1354043	1			T1	3707		T3	896		T4	7348
valid_sources[0x14]	1446035	1			T1	3809		T2	1		T3	902
valid_sources[0x15]	1477417	1			T1	3840		T2	1		T3	958
valid_sources[0x16]	1446928	1			T1	3799		T2	1		T3	914
valid_sources[0x17]	1471710	1			T1	3810		T3	866		T4	8278
valid_sources[0x18]	1358945	1			T1	3568		T3	870		T4	7457
valid_sources[0x19]	1361471	1			T1	4030		T2	1		T3	974
valid_sources[0x1a]	1359988	1			T1	3815		T3	968		T4	7645
valid_sources[0x1b]	1368695	1			T1	3778		T3	954		T4	7740
valid_sources[0x1c]	2020604	1			T1	3676		T3	971		T4	7082
valid_sources[0x1d]	3359345	1			T1	3900		T3	952		T4	7954
valid_sources[0x1e]	1363508	1			T1	3818		T3	879		T4	7666
valid_sources[0x1f]	1525880	1			T1	3794		T3	937		T4	8105
valid_sources[0x20]	2635185	1			T1	3717		T2	2		T3	1055
valid_sources[0x21]	4005139	1			T1	3751		T2	6		T3	887
valid_sources[0x22]	1578819	1			T1	3753		T2	1		T3	972
valid_sources[0x23]	2011012	1			T1	3851		T2	1		T3	861
valid_sources[0x24]	1363797	1			T1	3770		T3	946		T4	7212
valid_sources[0x25]	1362896	1			T1	3827		T2	2		T3	990
valid_sources[0x26]	1360401	1			T1	3734		T3	877		T4	7880
valid_sources[0x27]	2343609	1			T1	3822		T3	857		T4	7510
valid_sources[0x28]	1359565	1			T1	3828		T2	2		T3	880
valid_sources[0x29]	1363320	1			T1	3770		T3	943		T4	7174
valid_sources[0x2a]	1360919	1			T1	3933		T2	1		T3	928
valid_sources[0x2b]	1355786	1			T1	3658		T2	2		T3	920
valid_sources[0x2c]	1357868	1			T1	3938		T2	1		T3	930
valid_sources[0x2d]	2266782	1			T1	3806		T3	865		T4	7497
valid_sources[0x2e]	1358038	1			T1	3745		T3	961		T4	7678
valid_sources[0x2f]	1364030	1			T1	3610		T3	878		T4	7553
valid_sources[0x30]	1424575	1			T1	3696		T2	1		T3	1048
valid_sources[0x31]	1424766	1			T1	3962		T2	2		T3	931
valid_sources[0x32]	4109693	1			T1	3765		T2	4		T3	845
valid_sources[0x33]	1360780	1			T1	3850		T3	873		T4	7583
valid_sources[0x34]	1363229	1			T1	3864		T2	2		T3	985
valid_sources[0x35]	1476003	1			T1	3836		T3	1118		T4	7263
valid_sources[0x36]	2379099	1			T1	3805		T3	918		T4	7456
valid_sources[0x37]	1355889	1			T1	3849		T2	1		T3	858
valid_sources[0x38]	1369615	1			T1	3837		T2	1		T3	907
valid_sources[0x39]	3835280	1			T1	3673		T2	1		T3	1026
valid_sources[0x3a]	1466835	1			T1	3891		T3	929		T4	7522
valid_sources[0x3b]	1849404	1			T1	3853		T3	956		T4	7747
valid_sources[0x3c]	1477506	1			T1	3911		T2	2		T3	934
valid_sources[0x3d]	1364612	1			T1	3808		T2	2		T3	887
valid_sources[0x3e]	3173837	1			T1	3757		T2	1		T3	980
valid_sources[0x3f]	1366343	1			T1	3793		T2	2		T3	963
valid_sources[0x40]	1985192	1			T1	4015		T2	3		T3	947
valid_sources[0x41]	1358125	1			T1	3759		T3	927		T4	8002
valid_sources[0x42]	1362282	1			T1	3803		T2	2		T3	913
valid_sources[0x43]	1352690	1			T1	4040		T3	929		T4	7367
valid_sources[0x44]	1954381	1			T1	3855		T2	1		T3	873
valid_sources[0x45]	3176986	1			T1	3704		T2	1		T3	888
valid_sources[0x46]	1507181	1			T1	3881		T2	1		T3	879
valid_sources[0x47]	2012110	1			T1	3786		T2	2		T3	951
valid_sources[0x48]	1457622	1			T1	3733		T2	4		T3	938
valid_sources[0x49]	1354293	1			T1	3846		T2	1		T3	875
valid_sources[0x4a]	1353950	1			T1	3881		T3	882		T4	7122
valid_sources[0x4b]	3318885	1			T1	3969		T2	1		T3	974
valid_sources[0x4c]	1364233	1			T1	3867		T3	937		T4	7203
valid_sources[0x4d]	1540630	1			T1	3754		T2	2		T3	834
valid_sources[0x4e]	2004136	1			T1	3805		T3	874		T4	7560
valid_sources[0x4f]	1362784	1			T1	3934		T2	2		T3	954
valid_sources[0x50]	1362381	1			T1	3587		T2	1		T3	908
valid_sources[0x51]	1707793	1			T1	3913		T3	930		T4	8164
valid_sources[0x52]	3493582	1			T1	3569		T3	930		T4	8062
valid_sources[0x53]	1358185	1			T1	3796		T3	862		T4	7529
valid_sources[0x54]	1363544	1			T1	3759		T3	1023		T4	7726
valid_sources[0x55]	3860318	1			T1	3686		T3	921		T4	7597
valid_sources[0x56]	1366377	1			T1	3757		T3	986		T4	7430
valid_sources[0x57]	1361220	1			T1	3895		T3	894		T4	7632
valid_sources[0x58]	1408385	1			T1	3854		T3	1021		T4	7921
valid_sources[0x59]	1810383	1			T1	3810		T3	1071		T4	7545
valid_sources[0x5a]	1742034	1			T1	3683		T3	893		T4	7836
valid_sources[0x5b]	1362641	1			T1	3940		T3	888		T4	7419
valid_sources[0x5c]	1360231	1			T1	3802		T3	985		T4	7425
valid_sources[0x5d]	1359337	1			T1	3845		T3	957		T4	7403
valid_sources[0x5e]	1362786	1			T1	3780		T3	906		T4	7829
valid_sources[0x5f]	2162437	1			T1	3729		T3	907		T4	7968
valid_sources[0x60]	1359220	1			T1	3750		T3	954		T4	7505
valid_sources[0x61]	2211230	1			T1	3822		T2	5		T3	907
valid_sources[0x62]	1361547	1			T1	3862		T3	1046		T4	7091
valid_sources[0x63]	1361318	1			T1	3833		T3	924		T4	7269
valid_sources[0x64]	1359503	1			T1	3711		T3	947		T4	7678
valid_sources[0x65]	1360852	1			T1	3808		T3	894		T4	7108
valid_sources[0x66]	1359216	1			T1	3822		T2	1		T3	879
valid_sources[0x67]	3322645	1			T1	3933		T3	985		T4	7602
valid_sources[0x68]	1454956	1			T1	3813		T2	3		T3	971
valid_sources[0x69]	1360669	1			T1	3799		T2	1		T3	938
valid_sources[0x6a]	2204374	1			T1	3816		T3	1018		T4	7362
valid_sources[0x6b]	1367614	1			T1	3726		T3	929		T4	7670
valid_sources[0x6c]	1372445	1			T1	3757		T3	967		T4	7855
valid_sources[0x6d]	1488537	1			T1	3926		T2	2		T3	973
valid_sources[0x6e]	1356122	1			T1	3870		T2	4		T3	887
valid_sources[0x6f]	1365051	1			T1	3904		T3	998		T4	7444
valid_sources[0x70]	1361728	1			T1	3767		T3	902		T4	7416
valid_sources[0x71]	1359629	1			T1	3925		T2	1		T3	809
valid_sources[0x72]	1464777	1			T1	3941		T2	1		T3	907
valid_sources[0x73]	1356548	1			T1	3815		T3	973		T4	7283
valid_sources[0x74]	2235245	1			T1	3877		T2	1		T3	909
valid_sources[0x75]	1767286	1			T1	3866		T3	970		T4	7730
valid_sources[0x76]	1357455	1			T1	3715		T3	930		T4	7202
valid_sources[0x77]	1494261	1			T1	3670		T2	1		T3	1001
valid_sources[0x78]	1491158	1			T1	4074		T2	4		T3	943
valid_sources[0x79]	1457608	1			T1	3966		T2	1		T3	954
valid_sources[0x7a]	1352261	1			T1	3881		T3	893		T4	7681
valid_sources[0x7b]	1361514	1			T1	3772		T3	825		T4	7424
valid_sources[0x7c]	1811501	1			T1	3684		T3	884		T4	7378
valid_sources[0x7d]	1358635	1			T1	3657		T3	932		T4	7792
valid_sources[0x7e]	1359665	1			T1	3759		T2	1		T3	912
valid_sources[0x7f]	1363815	1			T1	3842		T2	1		T3	962
valid_sources[0x80]	3968687	1			T1	3789		T2	4		T3	983

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

72596779

1

T1

161948

T2

85

T3

42839

values[0x0]

all_enables

biggest_size

61716335

1

T1

131053

T2

51

T3

84643

values[0x1]

all_enables

biggest_size

53262023

1

T1

112074

T2

51

T3

84844