Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

263960815

1

T1

573137

T2

11

T3

25560

full_word

187775038

1

T1

405075

T2

187

T3

212326

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	451735543	1			T1	978212		T2	198		T3	237886
auto[TlIntgErrCmd]	103	1			T134	8		T135	1		T136	6
auto[TlIntgErrData]	104	1			T134	7		T135	9		T136	8
auto[TlIntgErrBoth]	103	1			T134	5		T135	10		T136	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

232718623

1

T1

511540

T2

90

T3

65977

auto[1]

219017230

1

T1

466672

T2

108

T3

171909

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	160071842	1			T1	349592		T2	5		T3	23138
auto[TlIntgErrNone]	partial	auto[1]	103888692	1			T1	223545		T2	6		T3	2422
auto[TlIntgErrNone]	full_word	auto[0]	72646642	1			T1	161948		T2	85		T3	42839
auto[TlIntgErrNone]	full_word	auto[1]	115128367	1			T1	243127		T2	102		T3	169487
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T134	4		T135	1		T180	2
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T134	3		T136	6		T180	4
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T187	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T134	1		T185	1		T187	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T134	2		T135	7		T136	3
auto[TlIntgErrData]	partial	auto[1]	47	1			T134	5		T135	1		T136	3
auto[TlIntgErrData]	full_word	auto[0]	7	1			T135	1		T136	2		T182	3
auto[TlIntgErrData]	full_word	auto[1]	5	1			T181	1		T187	1		T188	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T134	1		T135	8		T136	3
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T134	4		T135	2		T136	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T182	1		T183	1		T189	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T181	1		T182	1		T190	1