Unified Coverage Report :: Module :: prim_packer

Module : prim_packer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	100.00			92.31	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_msgfifo.u_packer	98.08	100.00	100.00			92.31	100.00

---

Module Instance : tb.dut.u_msgfifo.u_packer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	100.00			92.31	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.41	100.00	100.00	89.74		92.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.21	100.00			100.00	92.86	100.00	u_msgfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_pos_dupcnt.u_pos	89.74			89.74

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_packer

	Line No.	Total	Covered	Percent
TOTAL		62	62	100.00
ALWAYS	65	3	3	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	110	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
ALWAYS	120	3	3	100.00
ALWAYS	157	4	4	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
ALWAYS	185	9	9	100.00
ALWAYS	214	8	8	100.00
ALWAYS	235	3	3	100.00
ALWAYS	243	14	14	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	291	0	0
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	296	1	1	100.00
CONT_ASSIGN	299	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
66	1	1
67	1	1
72	1	1
110	1	1
111	1	1
112	1	1
115	1	1
120	1	1
122	1	1
124	1	1
			MISSING_ELSE
157	1	1
158	1	1
159	1	1
160	1	1
			MISSING_ELSE
165	1	1
166	1	1
170	1	1
171	1	1
174	1	1
175	1	1
178	1	1
180	1	1
185	1	1
187	1	1
188	1	1
192	1	1
193	1	1
197	1	1
198	1	1
202	1	1
203	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
221	1	1
222	1	1
235	1	1
236	1	1
238	1	1
243	1	1
245	1	1
246	1	1
248	1	1
250	1	1
251	1	1
253	1	1
258	1	1
259	1	1
261	1	1
262	1	1
264	1	1
266	1	1
267	1	1
279	1	1
283	1	1
291		unreachable
294	1	1
295	1	1
296	1	1
299		unreachable

---

Cond Coverage for Module : prim_packer

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       110
 EXPRESSION (ack_in && ((!ack_out)))
             ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T12,T61
1	1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (((!ack_in)) && ack_out)
             -----1-----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T61
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (ack_in && ack_out)
             ---1--    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T12,T61

 LINE       115
 EXPRESSION (g_pos_dupcnt.cnt_incr_en ? (8'(inmask_ones)) : (8'(OutW)))
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       159
 EXPRESSION (mask_i[i] == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       165
 EXPRESSION (valid_i & ready_o)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable	T67,T80,T49
1	1	Covered	T1,T2,T3

 LINE       166
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T80,T8,T49
1	1	Covered	T1,T2,T3

 LINE       170
 EXPRESSION (valid_i ? ((data_i >> lod_idx)) : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       171
 EXPRESSION (valid_i ? ((mask_i >> lod_idx)) : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       258
 EXPRESSION (pos_q == '0)
            ------1------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       283
 EXPRESSION ((int'(pos_q) >= OutW) ? 1'b1 : flush_valid)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable	T1,T2,T3

---

Branch Coverage for Module : prim_packer

	Line No.	Total	Covered	Percent
Branches		26	24	92.31
TERNARY	170	2	2	100.00
TERNARY	171	2	2	100.00
TERNARY	283	1	1	100.00
TERNARY	115	2	2	100.00
IF	159	2	2	100.00
CASE	185	5	4	80.00
IF	214	3	3	100.00
IF	235	2	2	100.00
CASE	248	5	4	80.00
IF	122	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	170	(valid_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	171	(valid_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	283	((int'(pos_q) >= OutW)) ? 

Branches:

-1-	Status	Tests
1	Unreachable	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	(g_pos_dupcnt.cnt_incr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	159	if ((mask_i[i] == 1'b1))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	185	case ({ack_in, ack_out})

Branches:

-1-	Status	Tests
2'b00	Covered	T1,T2,T3
2'b01	Covered	T1,T2,T3
2'b10	Covered	T1,T2,T3
2'b11	Covered	T2,T12,T61
default	Not Covered

	LineNo.	Expression
-1-:	214	if ((!rst_ni))
-2-:	217	if (flush_done)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	235	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	248	case (flush_st)
-2-:	250	if (flush_i)
-3-:	258	if ((pos_q == '0))

Branches:

-1-	-2-	-3-	Status	Tests
FlushIdle	1	-	Covered	T1,T3,T4
FlushIdle	0	-	Covered	T1,T2,T3
FlushSend	-	1	Covered	T1,T3,T4
FlushSend	-	0	Covered	T1,T3,T4
default	-	-	Not Covered

	LineNo.	Expression
-1-:	122	if ((pos_with_input > 8'(OutW)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_packer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	28	28	100.00	28	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	28	28	100.00	28	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataIStable_M	2147483647	451309	0	1025
DataOStableWhenPending_A	2147483647	685753	0	1025
ExFlushValid_M	2147483647	343139	0	0
ExcessiveDataStored_A	2147483647	52100	0	0
ExcessiveMaskStored_A	2147483647	52100	0	0
FlushFollowedByDone_A	2147483647	343139	0	1025
ValidIDeassertedOnFlush_M	2147483647	552003	0	0
ValidOAssertedForStoredDataGTEOutW_A	2147483647	48483612	0	0
ValidOPairedWidthReadyI_A	2147483647	685753	0	0
g_byte_assert.InputDividedBy8_A	1025	1025	0	0
g_byte_assert.OutputDividedBy8_A	1025	1025	0	0
g_byte_assert.g_byte_input_masking[0].InputMaskContiguous_A	2147483647	109740650	0	0
g_byte_assert.g_byte_input_masking[1].InputMaskContiguous_A	2147483647	109740650	0	0
g_byte_assert.g_byte_input_masking[2].InputMaskContiguous_A	2147483647	109740650	0	0
g_byte_assert.g_byte_input_masking[3].InputMaskContiguous_A	2147483647	109740650	0	0
g_byte_assert.g_byte_input_masking[4].InputMaskContiguous_A	2147483647	109740650	0	0
g_byte_assert.g_byte_input_masking[5].InputMaskContiguous_A	2147483647	109740650	0	0
g_byte_assert.g_byte_input_masking[6].InputMaskContiguous_A	2147483647	109740650	0	0
g_byte_assert.g_byte_input_masking[7].InputMaskContiguous_A	2147483647	109740650	0	0
g_byte_assert.g_byte_output_masking[0].OutputMaskContiguous_A	2147483647	48684752	0	0
g_byte_assert.g_byte_output_masking[1].OutputMaskContiguous_A	2147483647	48684752	0	0
g_byte_assert.g_byte_output_masking[2].OutputMaskContiguous_A	2147483647	48684752	0	0
g_byte_assert.g_byte_output_masking[3].OutputMaskContiguous_A	2147483647	48684752	0	0
g_byte_assert.g_byte_output_masking[4].OutputMaskContiguous_A	2147483647	48684752	0	0
g_byte_assert.g_byte_output_masking[5].OutputMaskContiguous_A	2147483647	48684752	0	0
g_byte_assert.g_byte_output_masking[6].OutputMaskContiguous_A	2147483647	48684752	0	0
g_byte_assert.g_byte_output_masking[7].OutputMaskContiguous_A	2147483647	48684752	0	0
gen_mask_assert.ContiguousOnesMask_M	2147483647	109740650	0	0

DataIStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	451309	0	1025
T8	836589	0	0	1
T9	0	504	0	0
T40	0	1487	0	0
T41	0	1836	0	0
T49	478521	15634	0	1
T50	886780	525	0	1
T51	923	0	0	1
T52	19993	0	0	1
T53	111827	0	0	1
T54	245820	0	0	1
T55	148145	0	0	1
T70	0	10134	0	0
T71	0	8429	0	0
T72	0	12	0	0
T80	730091	203	0	1
T114	0	4651	0	0
T115	605398	0	0	1

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	685753	0	1025
T8	836589	7276	0	1
T9	0	639	0	0
T40	0	1508	0	0
T49	478521	13752	0	1
T50	886780	525	0	1
T51	923	0	0	1
T52	19993	0	0	1
T53	111827	0	0	1
T54	245820	1162	0	1
T55	148145	0	0	1
T70	0	10232	0	0
T71	0	7646	0	0
T80	730091	301	0	1
T114	0	4749	0	0
T115	605398	0	0	1

ExFlushValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	343139	0	0
T1	975106	144	0	0
T2	3832	0	0	0
T3	233716	122	0	0
T4	148919	2265	0	0
T5	129485	46	0	0
T6	210638	157	0	0
T7	0	183	0	0
T10	1963	0	0	0
T11	39735	40	0	0
T12	104945	149	0	0
T13	73290	0	0	0
T19	0	2337	0	0
T36	0	142	0	0

ExcessiveDataStored_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	52100	0	0
T7	332423	0	0	0
T8	0	8	0	0
T12	104945	15	0	0
T13	73290	0	0	0
T14	0	4	0	0
T19	850664	0	0	0
T22	0	2	0	0
T36	108833	0	0	0
T49	0	746	0	0
T50	0	85	0	0
T53	0	1	0	0
T58	363806	0	0	0
T60	0	22	0	0
T61	589145	0	0	0
T67	0	1	0	0
T77	798852	0	0	0
T78	644840	0	0	0
T79	19181	0	0	0
T80	0	44	0	0

ExcessiveMaskStored_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	52100	0	0
T7	332423	0	0	0
T8	0	8	0	0
T12	104945	15	0	0
T13	73290	0	0	0
T14	0	4	0	0
T19	850664	0	0	0
T22	0	2	0	0
T36	108833	0	0	0
T49	0	746	0	0
T50	0	85	0	0
T53	0	1	0	0
T58	363806	0	0	0
T60	0	22	0	0
T61	589145	0	0	0
T67	0	1	0	0
T77	798852	0	0	0
T78	644840	0	0	0
T79	19181	0	0	0
T80	0	44	0	0

FlushFollowedByDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	343139	0	1025
T1	975106	144	0	1
T2	3832	0	0	1
T3	233716	122	0	1
T4	148919	2265	0	1
T5	129485	46	0	1
T6	210638	157	0	1
T7	0	183	0	0
T10	1963	0	0	1
T11	39735	40	0	1
T12	104945	149	0	1
T13	73290	0	0	1
T19	0	2337	0	0
T36	0	142	0	0

ValidIDeassertedOnFlush_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	552003	0	0
T1	975106	269	0	0
T2	3832	0	0	0
T3	233716	231	0	0
T4	148919	3155	0	0
T5	129485	79	0	0
T6	210638	286	0	0
T7	0	339	0	0
T10	1963	0	0	0
T11	39735	73	0	0
T12	104945	263	0	0
T13	73290	0	0	0
T19	0	3395	0	0
T36	0	269	0	0

ValidOAssertedForStoredDataGTEOutW_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48483612	0	0
T1	975106	100583	0	0
T2	3832	1	0	0
T3	233716	81656	0	0
T4	148919	194826	0	0
T5	129485	75	0	0
T6	210638	99441	0	0
T7	0	130424	0	0
T10	1963	0	0	0
T11	39735	68	0	0
T12	104945	9343	0	0
T13	73290	0	0	0
T36	0	5640	0	0

ValidOPairedWidthReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	685753	0	0
T8	836589	7276	0	0
T9	0	639	0	0
T40	0	1508	0	0
T49	478521	13752	0	0
T50	886780	525	0	0
T51	923	0	0	0
T52	19993	0	0	0
T53	111827	0	0	0
T54	245820	1162	0	0
T55	148145	0	0	0
T70	0	10232	0	0
T71	0	7646	0	0
T80	730091	301	0	0
T114	0	4749	0	0
T115	605398	0	0	0

g_byte_assert.InputDividedBy8_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

g_byte_assert.OutputDividedBy8_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

g_byte_assert.g_byte_input_masking[0].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	109740650	0	0
T1	975106	228973	0	0
T2	3832	1	0	0
T3	233716	163712	0	0
T4	148919	449343	0	0
T5	129485	254	0	0
T6	210638	230801	0	0
T7	0	261485	0	0
T10	1963	0	0	0
T11	39735	234	0	0
T12	104945	19553	0	0
T13	73290	0	0	0
T36	0	13595	0	0

g_byte_assert.g_byte_input_masking[1].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	109740650	0	0
T1	975106	228973	0	0
T2	3832	1	0	0
T3	233716	163712	0	0
T4	148919	449343	0	0
T5	129485	254	0	0
T6	210638	230801	0	0
T7	0	261485	0	0
T10	1963	0	0	0
T11	39735	234	0	0
T12	104945	19553	0	0
T13	73290	0	0	0
T36	0	13595	0	0

g_byte_assert.g_byte_input_masking[2].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	109740650	0	0
T1	975106	228973	0	0
T2	3832	1	0	0
T3	233716	163712	0	0
T4	148919	449343	0	0
T5	129485	254	0	0
T6	210638	230801	0	0
T7	0	261485	0	0
T10	1963	0	0	0
T11	39735	234	0	0
T12	104945	19553	0	0
T13	73290	0	0	0
T36	0	13595	0	0

g_byte_assert.g_byte_input_masking[3].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	109740650	0	0
T1	975106	228973	0	0
T2	3832	1	0	0
T3	233716	163712	0	0
T4	148919	449343	0	0
T5	129485	254	0	0
T6	210638	230801	0	0
T7	0	261485	0	0
T10	1963	0	0	0
T11	39735	234	0	0
T12	104945	19553	0	0
T13	73290	0	0	0
T36	0	13595	0	0

g_byte_assert.g_byte_input_masking[4].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	109740650	0	0
T1	975106	228973	0	0
T2	3832	1	0	0
T3	233716	163712	0	0
T4	148919	449343	0	0
T5	129485	254	0	0
T6	210638	230801	0	0
T7	0	261485	0	0
T10	1963	0	0	0
T11	39735	234	0	0
T12	104945	19553	0	0
T13	73290	0	0	0
T36	0	13595	0	0

g_byte_assert.g_byte_input_masking[5].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	109740650	0	0
T1	975106	228973	0	0
T2	3832	1	0	0
T3	233716	163712	0	0
T4	148919	449343	0	0
T5	129485	254	0	0
T6	210638	230801	0	0
T7	0	261485	0	0
T10	1963	0	0	0
T11	39735	234	0	0
T12	104945	19553	0	0
T13	73290	0	0	0
T36	0	13595	0	0

g_byte_assert.g_byte_input_masking[6].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	109740650	0	0
T1	975106	228973	0	0
T2	3832	1	0	0
T3	233716	163712	0	0
T4	148919	449343	0	0
T5	129485	254	0	0
T6	210638	230801	0	0
T7	0	261485	0	0
T10	1963	0	0	0
T11	39735	234	0	0
T12	104945	19553	0	0
T13	73290	0	0	0
T36	0	13595	0	0

g_byte_assert.g_byte_input_masking[7].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	109740650	0	0
T1	975106	228973	0	0
T2	3832	1	0	0
T3	233716	163712	0	0
T4	148919	449343	0	0
T5	129485	254	0	0
T6	210638	230801	0	0
T7	0	261485	0	0
T10	1963	0	0	0
T11	39735	234	0	0
T12	104945	19553	0	0
T13	73290	0	0	0
T36	0	13595	0	0

g_byte_assert.g_byte_output_masking[0].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48684752	0	0
T1	975106	100708	0	0
T2	3832	1	0	0
T3	233716	81765	0	0
T4	148919	195716	0	0
T5	129485	108	0	0
T6	210638	99570	0	0
T7	0	130580	0	0
T10	1963	0	0	0
T11	39735	101	0	0
T12	104945	9457	0	0
T13	73290	0	0	0
T36	0	5767	0	0

g_byte_assert.g_byte_output_masking[1].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48684752	0	0
T1	975106	100708	0	0
T2	3832	1	0	0
T3	233716	81765	0	0
T4	148919	195716	0	0
T5	129485	108	0	0
T6	210638	99570	0	0
T7	0	130580	0	0
T10	1963	0	0	0
T11	39735	101	0	0
T12	104945	9457	0	0
T13	73290	0	0	0
T36	0	5767	0	0

g_byte_assert.g_byte_output_masking[2].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48684752	0	0
T1	975106	100708	0	0
T2	3832	1	0	0
T3	233716	81765	0	0
T4	148919	195716	0	0
T5	129485	108	0	0
T6	210638	99570	0	0
T7	0	130580	0	0
T10	1963	0	0	0
T11	39735	101	0	0
T12	104945	9457	0	0
T13	73290	0	0	0
T36	0	5767	0	0

g_byte_assert.g_byte_output_masking[3].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48684752	0	0
T1	975106	100708	0	0
T2	3832	1	0	0
T3	233716	81765	0	0
T4	148919	195716	0	0
T5	129485	108	0	0
T6	210638	99570	0	0
T7	0	130580	0	0
T10	1963	0	0	0
T11	39735	101	0	0
T12	104945	9457	0	0
T13	73290	0	0	0
T36	0	5767	0	0

g_byte_assert.g_byte_output_masking[4].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48684752	0	0
T1	975106	100708	0	0
T2	3832	1	0	0
T3	233716	81765	0	0
T4	148919	195716	0	0
T5	129485	108	0	0
T6	210638	99570	0	0
T7	0	130580	0	0
T10	1963	0	0	0
T11	39735	101	0	0
T12	104945	9457	0	0
T13	73290	0	0	0
T36	0	5767	0	0

g_byte_assert.g_byte_output_masking[5].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48684752	0	0
T1	975106	100708	0	0
T2	3832	1	0	0
T3	233716	81765	0	0
T4	148919	195716	0	0
T5	129485	108	0	0
T6	210638	99570	0	0
T7	0	130580	0	0
T10	1963	0	0	0
T11	39735	101	0	0
T12	104945	9457	0	0
T13	73290	0	0	0
T36	0	5767	0	0

g_byte_assert.g_byte_output_masking[6].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48684752	0	0
T1	975106	100708	0	0
T2	3832	1	0	0
T3	233716	81765	0	0
T4	148919	195716	0	0
T5	129485	108	0	0
T6	210638	99570	0	0
T7	0	130580	0	0
T10	1963	0	0	0
T11	39735	101	0	0
T12	104945	9457	0	0
T13	73290	0	0	0
T36	0	5767	0	0

g_byte_assert.g_byte_output_masking[7].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48684752	0	0
T1	975106	100708	0	0
T2	3832	1	0	0
T3	233716	81765	0	0
T4	148919	195716	0	0
T5	129485	108	0	0
T6	210638	99570	0	0
T7	0	130580	0	0
T10	1963	0	0	0
T11	39735	101	0	0
T12	104945	9457	0	0
T13	73290	0	0	0
T36	0	5767	0	0

gen_mask_assert.ContiguousOnesMask_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	109740650	0	0
T1	975106	228973	0	0
T2	3832	1	0	0
T3	233716	163712	0	0
T4	148919	449343	0	0
T5	129485	254	0	0
T6	210638	230801	0	0
T7	0	261485	0	0
T10	1963	0	0	0
T11	39735	234	0	0
T12	104945	19553	0	0
T13	73290	0	0	0
T36	0	13595	0	0