Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	736576	0	0
entropy_period_rd_A	2147483647	1966	0	0
intr_enable_rd_A	2147483647	2540	0	0
prefix_0_rd_A	2147483647	1642	0	0
prefix_10_rd_A	2147483647	1808	0	0
prefix_1_rd_A	2147483647	1712	0	0
prefix_2_rd_A	2147483647	1847	0	0
prefix_3_rd_A	2147483647	1830	0	0
prefix_4_rd_A	2147483647	1691	0	0
prefix_5_rd_A	2147483647	1700	0	0
prefix_6_rd_A	2147483647	1779	0	0
prefix_7_rd_A	2147483647	1830	0	0
prefix_8_rd_A	2147483647	1934	0	0
prefix_9_rd_A	2147483647	1748	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	736576	0	0
T40	0	32106	0	0
T42	0	49724	0	0
T47	0	52524	0	0
T54	245820	34970	0	0
T55	148145	0	0	0
T56	9485	0	0	0
T57	155824	0	0	0
T72	696572	0	0	0
T140	0	15635	0	0
T141	0	18746	0	0
T142	0	131899	0	0
T143	0	28250	0	0
T144	0	57262	0	0
T145	0	87782	0	0
T146	320872	0	0	0
T147	101212	0	0	0
T148	572146	0	0	0
T149	754773	0	0	0
T150	50299	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1966	0	0
T97	6421	41	0	0
T98	6122	37	0	0
T111	3998	12	0	0
T134	22731	138	0	0
T161	11302	38	0	0
T162	1956	5	0	0
T163	7452	6	0	0
T164	7173	9	0	0
T165	26431	221	0	0
T166	10602	72	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2540	0	0
T97	6421	29	0	0
T98	6122	59	0	0
T111	3998	5	0	0
T134	22731	152	0	0
T138	1469	16	0	0
T161	11302	94	0	0
T162	1956	9	0	0
T163	7452	10	0	0
T167	1104	7	0	0
T168	1123	9	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1642	0	0
T97	6421	29	0	0
T98	6122	21	0	0
T111	3998	13	0	0
T134	22731	79	0	0
T135	21671	24	0	0
T161	11302	15	0	0
T163	7452	15	0	0
T164	7173	6	0	0
T165	26431	197	0	0
T166	10602	67	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1808	0	0
T97	6421	39	0	0
T98	6122	39	0	0
T111	3998	15	0	0
T134	22731	94	0	0
T161	11302	71	0	0
T162	1956	5	0	0
T163	7452	18	0	0
T164	7173	7	0	0
T165	26431	203	0	0
T166	10602	47	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1712	0	0
T97	6421	31	0	0
T98	6122	23	0	0
T111	3998	13	0	0
T134	22731	94	0	0
T161	11302	74	0	0
T162	1956	2	0	0
T163	7452	17	0	0
T164	7173	7	0	0
T165	26431	217	0	0
T166	10602	47	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1847	0	0
T97	6421	38	0	0
T98	6122	31	0	0
T111	3998	4	0	0
T134	22731	88	0	0
T161	11302	49	0	0
T162	1956	2	0	0
T163	7452	16	0	0
T164	7173	8	0	0
T165	26431	212	0	0
T166	10602	46	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1830	0	0
T97	6421	19	0	0
T98	6122	26	0	0
T111	3998	2	0	0
T134	22731	67	0	0
T161	11302	76	0	0
T162	1956	4	0	0
T163	7452	18	0	0
T164	7173	8	0	0
T165	26431	225	0	0
T166	10602	21	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1691	0	0
T97	6421	32	0	0
T98	6122	27	0	0
T111	3998	7	0	0
T134	22731	89	0	0
T161	11302	45	0	0
T162	1956	6	0	0
T163	7452	17	0	0
T164	7173	13	0	0
T165	26431	198	0	0
T166	10602	15	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1700	0	0
T97	6421	27	0	0
T98	6122	15	0	0
T111	3998	16	0	0
T134	22731	95	0	0
T135	21671	49	0	0
T161	11302	37	0	0
T163	7452	14	0	0
T164	7173	8	0	0
T165	26431	202	0	0
T166	10602	51	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1779	0	0
T97	6421	31	0	0
T98	6122	32	0	0
T111	3998	18	0	0
T134	22731	67	0	0
T135	21671	20	0	0
T161	11302	39	0	0
T163	7452	12	0	0
T164	7173	11	0	0
T165	26431	196	0	0
T166	10602	19	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1830	0	0
T97	6421	25	0	0
T98	6122	33	0	0
T111	3998	13	0	0
T134	22731	91	0	0
T135	21671	48	0	0
T161	11302	60	0	0
T163	7452	19	0	0
T164	7173	7	0	0
T165	26431	239	0	0
T166	10602	65	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1934	0	0
T97	6421	24	0	0
T98	6122	28	0	0
T111	3998	15	0	0
T134	22731	97	0	0
T135	21671	28	0	0
T161	11302	76	0	0
T163	7452	15	0	0
T164	7173	5	0	0
T165	26431	219	0	0
T166	10602	99	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1748	0	0
T97	6421	33	0	0
T98	6122	37	0	0
T111	3998	12	0	0
T134	22731	68	0	0
T161	11302	59	0	0
T162	1956	1	0	0
T163	7452	13	0	0
T164	7173	4	0	0
T165	26431	232	0	0
T166	10602	56	0	0