Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

264317027

1

T1

627

T2

135530

T3

68021

full_word

185342438

1

T1

1128

T2

927821

T3

361822

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	449659155	1			T1	1755		T2	228312		T3	429843
auto[TlIntgErrCmd]	113	1			T119	4		T120	3		T121	5
auto[TlIntgErrData]	100	1			T119	4		T120	13		T121	3
auto[TlIntgErrBoth]	97	1			T119	2		T120	4		T121	12

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

231486200

1

T1

717

T2

115167

T3

130758

auto[1]

218173265

1

T1

1038

T2

113145

T3

299085

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	159795396	1			T1	369		T2	822890		T3	64056
auto[TlIntgErrNone]	partial	auto[1]	104521342	1			T1	258		T2	532416		T3	3965
auto[TlIntgErrNone]	full_word	auto[0]	71690657	1			T1	348		T2	328785		T3	66702
auto[TlIntgErrNone]	full_word	auto[1]	113651760	1			T1	780		T2	599036		T3	295120
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T119	3		T121	1		T171	4
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T119	1		T120	3		T121	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T121	1		T172	1		T176	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T173	1		T177	1		T178	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T119	1		T120	5		T121	2
auto[TlIntgErrData]	partial	auto[1]	45	1			T119	2		T120	8		T121	1
auto[TlIntgErrData]	full_word	auto[0]	1	1			T173	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T119	1		T172	1		T174	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T119	1		T120	2		T121	3
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T119	1		T120	2		T121	6
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T121	1		T178	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T121	2		T179	1		T180	1