Unified Coverage Report :: Module :: prim_dom_and_2share

Module : prim_dom_and_2share

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[0].u_dom	100.00	100.00					100.00
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[1].u_dom	100.00	100.00					100.00
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[2].u_dom	100.00	100.00					100.00
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[3].u_dom	100.00	100.00					100.00
tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[4].u_dom	100.00	100.00					100.00

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[0].u_dom

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.37	100.00	98.75			98.73	100.00	u_keccak_p

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_inner_domain_regs.u_prim_flop_tab01	100.00	100.00				100.00
u_prim_flop_t01	100.00	100.00				100.00
u_prim_xor_q01	100.00	100.00
u_prim_xor_t01	100.00	100.00

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[1].u_dom

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.37	100.00	98.75			98.73	100.00	u_keccak_p

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_inner_domain_regs.u_prim_flop_tab01	100.00	100.00				100.00
u_prim_flop_t01	100.00	100.00				100.00
u_prim_xor_q01	100.00	100.00
u_prim_xor_t01	100.00	100.00

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[2].u_dom

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.37	100.00	98.75			98.73	100.00	u_keccak_p

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_inner_domain_regs.u_prim_flop_tab01	100.00	100.00				100.00
u_prim_flop_t01	100.00	100.00				100.00
u_prim_xor_q01	100.00	100.00
u_prim_xor_t01	100.00	100.00

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[3].u_dom

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.37	100.00	98.75			98.73	100.00	u_keccak_p

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_inner_domain_regs.u_prim_flop_tab01	100.00	100.00				100.00
u_prim_flop_t01	100.00	100.00				100.00
u_prim_xor_q01	100.00	100.00
u_prim_xor_t01	100.00	100.00

---

Module Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[4].u_dom

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.37	100.00	98.75			98.73	100.00	u_keccak_p

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_inner_domain_regs.u_prim_flop_tab01	100.00	100.00				100.00
u_prim_flop_t01	100.00	100.00				100.00
u_prim_xor_q01	100.00	100.00
u_prim_xor_t01	100.00	100.00

Line Coverage for Module : prim_dom_and_2share

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	57	1	1	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	110	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	142	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' or '../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
60	1	1
61	1	1
110	1	1
111	1	1
142	1	1

---

Assert Coverage for Module : prim_dom_and_2share

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
UnmaskedAndMatched_A	2147483647	767416200	0	0

UnmaskedAndMatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	767416200	0	0
T1	100270	7440	0	0
T2	1104510	3155280	0	0
T3	1510870	2082720	0	0
T4	588500	527040	0	0
T5	739260	98160	0	0
T6	559405	276000	0	0
T7	538665	1302480	0	0
T8	52480	7440	0	0
T9	3902615	170400	0	0
T10	3579270	124080	0	0

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[0].u_dom

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	57	1	1	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	110	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	142	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' or '../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
60	1	1
61	1	1
110	1	1
111	1	1
142	1	1

---

Assert Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[0].u_dom

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
UnmaskedAndMatched_A	2147483647	153483240	0	0

UnmaskedAndMatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	153483240	0	0
T1	20054	1488	0	0
T2	220902	631056	0	0
T3	302174	416544	0	0
T4	117700	105408	0	0
T5	147852	19632	0	0
T6	111881	55200	0	0
T7	107733	260496	0	0
T8	10496	1488	0	0
T9	780523	34080	0	0
T10	715854	24816	0	0

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[1].u_dom

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	57	1	1	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	110	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	142	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' or '../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
60	1	1
61	1	1
110	1	1
111	1	1
142	1	1

---

Assert Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[1].u_dom

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
UnmaskedAndMatched_A	2147483647	153483240	0	0

UnmaskedAndMatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	153483240	0	0
T1	20054	1488	0	0
T2	220902	631056	0	0
T3	302174	416544	0	0
T4	117700	105408	0	0
T5	147852	19632	0	0
T6	111881	55200	0	0
T7	107733	260496	0	0
T8	10496	1488	0	0
T9	780523	34080	0	0
T10	715854	24816	0	0

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[2].u_dom

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	57	1	1	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	110	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	142	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' or '../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
60	1	1
61	1	1
110	1	1
111	1	1
142	1	1

---

Assert Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[2].u_dom

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
UnmaskedAndMatched_A	2147483647	153483240	0	0

UnmaskedAndMatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	153483240	0	0
T1	20054	1488	0	0
T2	220902	631056	0	0
T3	302174	416544	0	0
T4	117700	105408	0	0
T5	147852	19632	0	0
T6	111881	55200	0	0
T7	107733	260496	0	0
T8	10496	1488	0	0
T9	780523	34080	0	0
T10	715854	24816	0	0

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[3].u_dom

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	57	1	1	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	110	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	142	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' or '../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
60	1	1
61	1	1
110	1	1
111	1	1
142	1	1

---

Assert Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[3].u_dom

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
UnmaskedAndMatched_A	2147483647	153483240	0	0

UnmaskedAndMatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	153483240	0	0
T1	20054	1488	0	0
T2	220902	631056	0	0
T3	302174	416544	0	0
T4	117700	105408	0	0
T5	147852	19632	0	0
T6	111881	55200	0	0
T7	107733	260496	0	0
T8	10496	1488	0	0
T9	780523	34080	0	0
T10	715854	24816	0	0

Line Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[4].u_dom

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	57	1	1	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	110	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	142	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' or '../src/lowrisc_prim_prim_dom_and_2share_0.1/rtl/prim_dom_and_2share.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
60	1	1
61	1	1
110	1	1
111	1	1
142	1	1

---

Assert Coverage for Instance : tb.dut.u_sha3.u_keccak.u_keccak_p.g_2share_chi.g_chi_w[4].u_dom

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
UnmaskedAndMatched_A	2147483647	153483240	0	0

UnmaskedAndMatched_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	153483240	0	0
T1	20054	1488	0	0
T2	220902	631056	0	0
T3	302174	416544	0	0
T4	117700	105408	0	0
T5	147852	19632	0	0
T6	111881	55200	0	0
T7	107733	260496	0	0
T8	10496	1488	0	0
T9	780523	34080	0	0
T10	715854	24816	0	0