Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	2147483647	346575	0	0
RunThenComplete_M	2147483647	3050690	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	346575	0	0
T1	20054	9	0	0
T2	220902	2337	0	0
T3	302174	198	0	0
T4	117700	197	0	0
T5	147852	9	0	0
T6	111881	126	0	0
T7	107733	246	0	0
T8	10496	9	0	0
T9	780523	91	0	0
T10	715854	105	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3050690	0	0
T1	20054	31	0	0
T2	220902	13147	0	0
T3	302174	8016	0	0
T4	117700	1774	0	0
T5	147852	382	0	0
T6	111881	724	0	0
T7	107733	5427	0	0
T8	10496	31	0	0
T9	780523	456	0	0
T10	715854	517	0	0