Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	910473	0	0
entropy_period_rd_A	2147483647	1961	0	0
intr_enable_rd_A	2147483647	2626	0	0
prefix_0_rd_A	2147483647	2251	0	0
prefix_10_rd_A	2147483647	2263	0	0
prefix_1_rd_A	2147483647	2177	0	0
prefix_2_rd_A	2147483647	2198	0	0
prefix_3_rd_A	2147483647	2188	0	0
prefix_4_rd_A	2147483647	2082	0	0
prefix_5_rd_A	2147483647	2190	0	0
prefix_6_rd_A	2147483647	2102	0	0
prefix_7_rd_A	2147483647	2129	0	0
prefix_8_rd_A	2147483647	2151	0	0
prefix_9_rd_A	2147483647	2135	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	910473	0	0
T22	5561	0	0	0
T36	101992	128172	0	0
T37	223941	35120	0	0
T38	485152	0	0	0
T39	102158	0	0	0
T52	233063	0	0	0
T57	0	41150	0	0
T58	0	4896	0	0
T60	1037	0	0	0
T101	454457	0	0	0
T102	20447	0	0	0
T125	0	72517	0	0
T126	0	35718	0	0
T127	0	49947	0	0
T128	0	96758	0	0
T129	0	92279	0	0
T130	0	19387	0	0
T131	182233	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1961	0	0
T67	494187	0	0	0
T80	0	18	0	0
T81	0	11	0	0
T88	0	5	0	0
T119	0	45	0	0
T121	0	55	0	0
T143	817998	18	0	0
T144	0	9	0	0
T145	0	4	0	0
T146	0	8	0	0
T147	0	8	0	0
T148	10600	0	0	0
T149	391220	0	0	0
T150	132723	0	0	0
T151	859583	0	0	0
T152	595990	0	0	0
T153	102057	0	0	0
T154	189530	0	0	0
T155	922831	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2626	0	0
T67	494187	0	0	0
T80	0	25	0	0
T81	0	11	0	0
T119	0	38	0	0
T123	0	5	0	0
T143	817998	18	0	0
T144	0	2	0	0
T145	0	12	0	0
T146	0	6	0	0
T147	0	6	0	0
T148	10600	0	0	0
T149	391220	0	0	0
T150	132723	0	0	0
T151	859583	0	0	0
T152	595990	0	0	0
T153	102057	0	0	0
T154	189530	0	0	0
T155	922831	0	0	0
T156	0	3	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2251	0	0
T67	494187	0	0	0
T80	0	12	0	0
T81	0	8	0	0
T88	0	7	0	0
T119	0	19	0	0
T121	0	52	0	0
T143	817998	18	0	0
T145	0	9	0	0
T146	0	6	0	0
T147	0	5	0	0
T148	10600	0	0	0
T149	391220	0	0	0
T150	132723	0	0	0
T151	859583	0	0	0
T152	595990	0	0	0
T153	102057	0	0	0
T154	189530	0	0	0
T155	922831	0	0	0
T157	0	10	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2263	0	0
T67	494187	0	0	0
T80	0	13	0	0
T81	0	19	0	0
T88	0	1	0	0
T119	0	28	0	0
T121	0	41	0	0
T143	817998	17	0	0
T144	0	10	0	0
T145	0	11	0	0
T146	0	10	0	0
T147	0	12	0	0
T148	10600	0	0	0
T149	391220	0	0	0
T150	132723	0	0	0
T151	859583	0	0	0
T152	595990	0	0	0
T153	102057	0	0	0
T154	189530	0	0	0
T155	922831	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2177	0	0
T67	494187	0	0	0
T80	0	27	0	0
T81	0	11	0	0
T88	0	1	0	0
T119	0	11	0	0
T121	0	33	0	0
T143	817998	8	0	0
T144	0	16	0	0
T145	0	6	0	0
T146	0	5	0	0
T147	0	8	0	0
T148	10600	0	0	0
T149	391220	0	0	0
T150	132723	0	0	0
T151	859583	0	0	0
T152	595990	0	0	0
T153	102057	0	0	0
T154	189530	0	0	0
T155	922831	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2198	0	0
T67	494187	0	0	0
T80	0	21	0	0
T81	0	19	0	0
T88	0	7	0	0
T119	0	4	0	0
T121	0	70	0	0
T143	817998	17	0	0
T144	0	7	0	0
T145	0	3	0	0
T146	0	8	0	0
T147	0	18	0	0
T148	10600	0	0	0
T149	391220	0	0	0
T150	132723	0	0	0
T151	859583	0	0	0
T152	595990	0	0	0
T153	102057	0	0	0
T154	189530	0	0	0
T155	922831	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2188	0	0
T67	494187	0	0	0
T80	0	12	0	0
T81	0	23	0	0
T88	0	9	0	0
T119	0	36	0	0
T121	0	40	0	0
T143	817998	6	0	0
T144	0	10	0	0
T145	0	6	0	0
T146	0	9	0	0
T147	0	8	0	0
T148	10600	0	0	0
T149	391220	0	0	0
T150	132723	0	0	0
T151	859583	0	0	0
T152	595990	0	0	0
T153	102057	0	0	0
T154	189530	0	0	0
T155	922831	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2082	0	0
T67	494187	0	0	0
T80	0	10	0	0
T81	0	12	0	0
T88	0	13	0	0
T119	0	14	0	0
T121	0	39	0	0
T143	817998	15	0	0
T144	0	21	0	0
T145	0	12	0	0
T146	0	11	0	0
T147	0	7	0	0
T148	10600	0	0	0
T149	391220	0	0	0
T150	132723	0	0	0
T151	859583	0	0	0
T152	595990	0	0	0
T153	102057	0	0	0
T154	189530	0	0	0
T155	922831	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2190	0	0
T67	494187	0	0	0
T80	0	18	0	0
T81	0	14	0	0
T88	0	3	0	0
T119	0	21	0	0
T121	0	37	0	0
T143	817998	30	0	0
T144	0	14	0	0
T145	0	4	0	0
T146	0	2	0	0
T147	0	9	0	0
T148	10600	0	0	0
T149	391220	0	0	0
T150	132723	0	0	0
T151	859583	0	0	0
T152	595990	0	0	0
T153	102057	0	0	0
T154	189530	0	0	0
T155	922831	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2102	0	0
T67	494187	0	0	0
T80	0	18	0	0
T81	0	8	0	0
T88	0	7	0	0
T119	0	14	0	0
T121	0	53	0	0
T143	817998	9	0	0
T144	0	11	0	0
T145	0	6	0	0
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T148	10600	0	0	0
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T153	102057	0	0	0
T154	189530	0	0	0
T155	922831	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2129	0	0
T67	494187	0	0	0
T80	0	18	0	0
T81	0	9	0	0
T88	0	2	0	0
T119	0	6	0	0
T121	0	38	0	0
T143	817998	3	0	0
T144	0	12	0	0
T145	0	1	0	0
T146	0	6	0	0
T147	0	1	0	0
T148	10600	0	0	0
T149	391220	0	0	0
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T153	102057	0	0	0
T154	189530	0	0	0
T155	922831	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2151	0	0
T67	494187	0	0	0
T80	0	17	0	0
T81	0	10	0	0
T88	0	9	0	0
T119	0	4	0	0
T121	0	27	0	0
T143	817998	15	0	0
T144	0	17	0	0
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T153	102057	0	0	0
T154	189530	0	0	0
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prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2135	0	0
T67	494187	0	0	0
T80	0	13	0	0
T81	0	14	0	0
T88	0	15	0	0
T119	0	40	0	0
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T144	0	6	0	0
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