Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	258398011	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

184760921

1

T1

203

T2

1114

T3

251966

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	229365728	1			T1	82		T2	779		T3	331165
values[0x0]	102657395	1			T1	81		T2	502		T3	157216
values[0x1]	111135809	1			T1	63		T2	597		T3	171045

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	200707006	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

242451926

1

T1

207

T2

1298

T3

341650

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2117151	1			T2	4		T3	2579		T10	2310
valid_sources[0x01]	3191973	1			T2	7		T3	2551		T10	2825
valid_sources[0x02]	1308107	1			T2	8		T3	2617		T10	2666
valid_sources[0x03]	2345567	1			T2	11		T3	2598		T10	2288
valid_sources[0x04]	1308488	1			T2	6		T3	2609		T10	2750
valid_sources[0x05]	1327711	1			T2	5		T3	2567		T10	2412
valid_sources[0x06]	1959175	1			T2	9		T3	2591		T10	2570
valid_sources[0x07]	3322550	1			T2	10		T3	2580		T10	2451
valid_sources[0x08]	1309724	1			T2	12		T3	2560		T10	2610
valid_sources[0x09]	1313263	1			T2	4		T3	2636		T10	2283
valid_sources[0x0a]	1309221	1			T2	12		T3	2633		T10	2552
valid_sources[0x0b]	1302011	1			T2	9		T3	2620		T10	2531
valid_sources[0x0c]	1302464	1			T2	12		T3	2565		T10	2898
valid_sources[0x0d]	1308143	1			T2	5		T3	2629		T10	2272
valid_sources[0x0e]	1312588	1			T2	11		T3	2468		T10	2512
valid_sources[0x0f]	2153482	1			T2	5		T3	2541		T10	2568
valid_sources[0x10]	2207852	1			T2	10		T3	2673		T10	2636
valid_sources[0x11]	1319393	1			T2	7		T3	2503		T10	2383
valid_sources[0x12]	1446134	1			T2	9		T3	2603		T10	2407
valid_sources[0x13]	1473810	1			T2	11		T3	2658		T10	2614
valid_sources[0x14]	1320493	1			T2	3		T3	2571		T10	2333
valid_sources[0x15]	1309102	1			T2	7		T3	2613		T10	2451
valid_sources[0x16]	1310289	1			T2	3		T3	2660		T10	2353
valid_sources[0x17]	1885173	1			T2	2		T3	2657		T10	2519
valid_sources[0x18]	1308609	1			T2	10		T3	2514		T10	2295
valid_sources[0x19]	1311200	1			T2	11		T3	2591		T10	2535
valid_sources[0x1a]	2227483	1			T2	11		T3	2594		T10	2361
valid_sources[0x1b]	1394769	1			T2	9		T3	2488		T10	2567
valid_sources[0x1c]	1311314	1			T2	9		T3	2474		T10	2742
valid_sources[0x1d]	1776735	1			T2	7		T3	2659		T10	2320
valid_sources[0x1e]	1319664	1			T2	13		T3	2681		T10	2372
valid_sources[0x1f]	1317989	1			T2	9		T3	2552		T10	2690
valid_sources[0x20]	1312040	1			T2	10		T3	2460		T10	2470
valid_sources[0x21]	1306844	1			T2	11		T3	2596		T10	2439
valid_sources[0x22]	1890197	1			T2	8		T3	2613		T10	2541
valid_sources[0x23]	1353550	1			T2	5		T3	2553		T10	2404
valid_sources[0x24]	1455764	1			T2	3		T3	2545		T10	2654
valid_sources[0x25]	1352537	1			T2	8		T3	2553		T10	2629
valid_sources[0x26]	1510165	1			T2	11		T3	2512		T10	2547
valid_sources[0x27]	1306433	1			T2	11		T3	2533		T10	2493
valid_sources[0x28]	1311120	1			T2	6		T3	2598		T10	2506
valid_sources[0x29]	1307937	1			T2	5		T3	2619		T10	2532
valid_sources[0x2a]	1313517	1			T2	4		T3	2673		T10	2418
valid_sources[0x2b]	1315952	1			T2	3		T3	2616		T10	2522
valid_sources[0x2c]	2166274	1			T2	5		T3	2553		T10	2662
valid_sources[0x2d]	2750003	1			T2	7		T3	2545		T10	2667
valid_sources[0x2e]	1307456	1			T2	12		T3	2560		T10	2564
valid_sources[0x2f]	1320198	1			T2	3		T3	2559		T10	2683
valid_sources[0x30]	1317100	1			T2	10		T3	2546		T10	2506
valid_sources[0x31]	1313043	1			T2	10		T3	2597		T10	2526
valid_sources[0x32]	1304257	1			T1	1		T2	13		T3	2627
valid_sources[0x33]	2245254	1			T2	8		T3	2548		T10	2619
valid_sources[0x34]	1307057	1			T2	2		T3	2545		T10	2415
valid_sources[0x35]	3694226	1			T2	1		T3	2511		T10	2506
valid_sources[0x36]	2715552	1			T2	8		T3	2598		T10	2353
valid_sources[0x37]	1311220	1			T2	7		T3	2562		T10	2744
valid_sources[0x38]	1415825	1			T2	6		T3	2563		T10	2670
valid_sources[0x39]	1490237	1			T2	14		T3	2615		T10	2723
valid_sources[0x3a]	1310720	1			T2	13		T3	2600		T10	2397
valid_sources[0x3b]	3270166	1			T2	11		T3	2612		T10	2671
valid_sources[0x3c]	1309155	1			T2	10		T3	2490		T10	2671
valid_sources[0x3d]	1316223	1			T2	8		T3	2693		T10	2555
valid_sources[0x3e]	1310524	1			T2	7		T3	2466		T10	2612
valid_sources[0x3f]	1305263	1			T2	6		T3	2651		T10	2433
valid_sources[0x40]	3711514	1			T2	8		T3	2576		T10	2465
valid_sources[0x41]	1313231	1			T2	4		T3	2597		T10	2769
valid_sources[0x42]	1304892	1			T2	7		T3	2552		T10	2605
valid_sources[0x43]	1310150	1			T2	4		T3	2505		T10	2526
valid_sources[0x44]	1308897	1			T2	8		T3	2619		T10	2317
valid_sources[0x45]	1310152	1			T2	5		T3	2557		T10	2391
valid_sources[0x46]	1299696	1			T2	8		T3	2535		T10	2609
valid_sources[0x47]	1303017	1			T2	4		T3	2443		T10	2501
valid_sources[0x48]	1304983	1			T2	13		T3	2582		T4	1778
valid_sources[0x49]	1308513	1			T2	10		T3	2613		T10	2699
valid_sources[0x4a]	1309607	1			T2	14		T3	2522		T10	2604
valid_sources[0x4b]	1316921	1			T2	3		T3	2541		T10	2711
valid_sources[0x4c]	1398817	1			T2	5		T3	2586		T10	2615
valid_sources[0x4d]	1318047	1			T2	6		T3	2545		T10	2495
valid_sources[0x4e]	3298597	1			T2	10		T3	2682		T10	2291
valid_sources[0x4f]	1309352	1			T2	7		T3	2602		T10	2543
valid_sources[0x50]	1305629	1			T2	14		T3	2644		T10	2560
valid_sources[0x51]	1300873	1			T2	2		T3	2555		T10	2423
valid_sources[0x52]	3643052	1			T2	6		T3	2582		T10	2688
valid_sources[0x53]	1301013	1			T2	4		T3	2555		T10	2565
valid_sources[0x54]	2150198	1			T2	13		T3	2584		T10	2610
valid_sources[0x55]	1521755	1			T2	8		T3	2636		T10	2582
valid_sources[0x56]	1305345	1			T2	5		T3	2507		T10	2797
valid_sources[0x57]	3050258	1			T2	4		T3	2617		T10	2466
valid_sources[0x58]	1307528	1			T2	4		T3	2626		T10	2369
valid_sources[0x59]	1397732	1			T2	5		T3	2601		T10	2522
valid_sources[0x5a]	2058483	1			T2	14		T3	2566		T10	2696
valid_sources[0x5b]	1309009	1			T2	14		T3	2567		T10	2538
valid_sources[0x5c]	1315243	1			T2	5		T3	2523		T10	2529
valid_sources[0x5d]	1342987	1			T2	3		T3	2550		T10	2627
valid_sources[0x5e]	1317121	1			T2	8		T3	2500		T10	2662
valid_sources[0x5f]	1307366	1			T2	5		T3	2664		T10	2564
valid_sources[0x60]	2162828	1			T1	1		T2	9		T3	2490
valid_sources[0x61]	3562255	1			T2	12		T3	2667		T10	2596
valid_sources[0x62]	1305594	1			T2	1		T3	2553		T10	2342
valid_sources[0x63]	1307347	1			T2	7		T3	2663		T10	2728
valid_sources[0x64]	3470578	1			T2	12		T3	2630		T10	2591
valid_sources[0x65]	1605655	1			T2	1		T3	2603		T10	2344
valid_sources[0x66]	1966672	1			T2	7		T3	2610		T10	2385
valid_sources[0x67]	1400403	1			T2	3		T3	2629		T10	2310
valid_sources[0x68]	1313298	1			T2	14		T3	2550		T10	2450
valid_sources[0x69]	1951125	1			T2	6		T3	2593		T10	2568
valid_sources[0x6a]	2781447	1			T2	6		T3	2494		T10	2436
valid_sources[0x6b]	2157351	1			T2	8		T3	2595		T10	2289
valid_sources[0x6c]	2051072	1			T2	5		T3	2600		T10	2467
valid_sources[0x6d]	1316580	1			T2	3		T3	2599		T10	2337
valid_sources[0x6e]	1543479	1			T1	223		T2	8		T3	2642
valid_sources[0x6f]	2139566	1			T2	7		T3	2599		T10	2386
valid_sources[0x70]	1305023	1			T2	5		T3	2613		T10	2668
valid_sources[0x71]	3280659	1			T2	12		T3	2524		T10	2662
valid_sources[0x72]	1300392	1			T2	13		T3	2644		T10	2552
valid_sources[0x73]	1314412	1			T2	8		T3	2523		T10	2420
valid_sources[0x74]	1792802	1			T2	5		T3	2678		T10	2672
valid_sources[0x75]	1949094	1			T2	6		T3	2549		T10	2469
valid_sources[0x76]	1562514	1			T2	5		T3	2569		T10	2414
valid_sources[0x77]	4297409	1			T2	7		T3	2581		T10	2325
valid_sources[0x78]	3627190	1			T2	4		T3	2591		T10	2471
valid_sources[0x79]	1310356	1			T2	12		T3	2457		T10	2362
valid_sources[0x7a]	1303377	1			T2	12		T3	2575		T10	2551
valid_sources[0x7b]	1318466	1			T2	9		T3	2561		T10	2870
valid_sources[0x7c]	1304057	1			T2	6		T3	2609		T10	2592
valid_sources[0x7d]	1306834	1			T2	5		T3	2563		T10	2523
valid_sources[0x7e]	1315773	1			T2	2		T3	2569		T10	2468
valid_sources[0x7f]	1305149	1			T2	3		T3	2608		T10	2648
valid_sources[0x80]	1306770	1			T2	12		T3	2554		T10	2705

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

71314279

1

T1

72

T2

351

T3

88806

values[0x0]

all_enables

biggest_size

60907028

1

T1

74

T2

374

T3

88501

values[0x1]

all_enables

biggest_size

52539614

1

T1

57

T2

389

T3

74659