Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

262674526

1

T1

23

T2

764

T3

407460

full_word

185030541

1

T1

203

T2

1114

T3

251966

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	447704757	1			T1	226		T2	1878		T3	659426
auto[TlIntgErrCmd]	117	1			T144	6		T145	2		T146	3
auto[TlIntgErrData]	90	1			T144	4		T145	4		T146	6
auto[TlIntgErrBoth]	103	1			T144	10		T145	4		T146	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

230194819

1

T1

82

T2

779

T3

331165

auto[1]

217510248

1

T1

144

T2

1099

T3

328261

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	158812407	1			T1	10		T2	428		T3	242359
auto[TlIntgErrNone]	partial	auto[1]	103861839	1			T1	13		T2	336		T3	165101
auto[TlIntgErrNone]	full_word	auto[0]	71382291	1			T1	72		T2	351		T3	88806
auto[TlIntgErrNone]	full_word	auto[1]	113648220	1			T1	131		T2	763		T3	163160
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T144	2		T146	2		T199	2
auto[TlIntgErrCmd]	partial	auto[1]	74	1			T144	4		T145	2		T199	6
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T203	1		T204	1		T205	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T146	1		T199	1		T202	1
auto[TlIntgErrData]	partial	auto[0]	29	1			T144	3		T146	4		T199	1
auto[TlIntgErrData]	partial	auto[1]	49	1			T144	1		T145	3		T146	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T145	1		T202	1		T206	2
auto[TlIntgErrData]	full_word	auto[1]	5	1			T200	1		T207	1		T208	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T144	5		T199	3		T203	1
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T144	4		T145	2		T199	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T144	1		T145	1		T200	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T145	1		T146	1		T209	1