Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	2147483647	342937	0	0
RunThenComplete_M	2147483647	3053147	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	342937	0	0
T2	23226	9	0	0
T3	157672	310	0	0
T4	26800	9	0	0
T5	171461	111	0	0
T10	628216	310	0	0
T11	24139	9	0	0
T12	981	0	0	0
T13	632863	2265	0	0
T14	151449	310	0	0
T61	193960	374	0	0
T62	0	9	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3053147	0	0
T2	23226	31	0	0
T3	157672	5462	0	0
T4	26800	31	0	0
T5	171461	4599	0	0
T10	628216	5462	0	0
T11	24139	31	0	0
T12	981	0	0	0
T13	632863	12979	0	0
T14	151449	5462	0	0
T61	193960	5526	0	0
T62	0	31	0	0