Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	993206	0	0
entropy_period_rd_A	2147483647	2785	0	0
intr_enable_rd_A	2147483647	3627	0	0
prefix_0_rd_A	2147483647	2301	0	0
prefix_10_rd_A	2147483647	2524	0	0
prefix_1_rd_A	2147483647	2770	0	0
prefix_2_rd_A	2147483647	2517	0	0
prefix_3_rd_A	2147483647	2773	0	0
prefix_4_rd_A	2147483647	2683	0	0
prefix_5_rd_A	2147483647	2599	0	0
prefix_6_rd_A	2147483647	2630	0	0
prefix_7_rd_A	2147483647	2572	0	0
prefix_8_rd_A	2147483647	2672	0	0
prefix_9_rd_A	2147483647	2720	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	993206	0	0
T31	0	14832	0	0
T34	35983	0	0	0
T35	212623	0	0	0
T66	0	136398	0	0
T67	0	156288	0	0
T81	495235	0	0	0
T84	123557	10653	0	0
T140	0	93890	0	0
T150	0	12984	0	0
T151	0	59289	0	0
T152	0	60386	0	0
T153	0	41362	0	0
T154	0	159646	0	0
T155	203327	0	0	0
T156	98558	0	0	0
T157	435025	0	0	0
T158	148767	0	0	0
T159	656463	0	0	0
T160	197239	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2785	0	0
T40	716774	0	0	0
T67	199283	316	0	0
T144	0	117	0	0
T150	0	64	0	0
T152	0	159	0	0
T169	0	72	0	0
T170	0	15	0	0
T171	0	8	0	0
T172	0	7	0	0
T173	0	10	0	0
T174	0	6	0	0
T175	122776	0	0	0
T176	674853	0	0	0
T177	230835	0	0	0
T178	105315	0	0	0
T179	151539	0	0	0
T180	481463	0	0	0
T181	114189	0	0	0
T182	972453	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3627	0	0
T40	716774	0	0	0
T67	199283	345	0	0
T144	0	210	0	0
T149	0	7	0	0
T150	0	45	0	0
T152	0	170	0	0
T169	0	54	0	0
T170	0	21	0	0
T172	0	25	0	0
T173	0	19	0	0
T175	122776	0	0	0
T176	674853	0	0	0
T177	230835	0	0	0
T178	105315	0	0	0
T179	151539	0	0	0
T180	481463	0	0	0
T181	114189	0	0	0
T182	972453	0	0	0
T183	0	21	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2301	0	0
T40	716774	0	0	0
T67	199283	333	0	0
T144	0	79	0	0
T150	0	18	0	0
T152	0	113	0	0
T169	0	56	0	0
T170	0	25	0	0
T171	0	3	0	0
T172	0	8	0	0
T173	0	5	0	0
T174	0	5	0	0
T175	122776	0	0	0
T176	674853	0	0	0
T177	230835	0	0	0
T178	105315	0	0	0
T179	151539	0	0	0
T180	481463	0	0	0
T181	114189	0	0	0
T182	972453	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2524	0	0
T40	716774	0	0	0
T67	199283	348	0	0
T144	0	83	0	0
T150	0	45	0	0
T152	0	130	0	0
T169	0	29	0	0
T170	0	15	0	0
T171	0	5	0	0
T172	0	3	0	0
T173	0	12	0	0
T174	0	3	0	0
T175	122776	0	0	0
T176	674853	0	0	0
T177	230835	0	0	0
T178	105315	0	0	0
T179	151539	0	0	0
T180	481463	0	0	0
T181	114189	0	0	0
T182	972453	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2770	0	0
T40	716774	0	0	0
T67	199283	377	0	0
T111	0	2	0	0
T144	0	74	0	0
T150	0	47	0	0
T152	0	197	0	0
T169	0	48	0	0
T170	0	21	0	0
T171	0	6	0	0
T172	0	13	0	0
T173	0	8	0	0
T175	122776	0	0	0
T176	674853	0	0	0
T177	230835	0	0	0
T178	105315	0	0	0
T179	151539	0	0	0
T180	481463	0	0	0
T181	114189	0	0	0
T182	972453	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2517	0	0
T40	716774	0	0	0
T67	199283	351	0	0
T111	0	10	0	0
T144	0	84	0	0
T150	0	21	0	0
T152	0	123	0	0
T169	0	34	0	0
T170	0	16	0	0
T171	0	5	0	0
T172	0	12	0	0
T173	0	6	0	0
T175	122776	0	0	0
T176	674853	0	0	0
T177	230835	0	0	0
T178	105315	0	0	0
T179	151539	0	0	0
T180	481463	0	0	0
T181	114189	0	0	0
T182	972453	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2773	0	0
T40	716774	0	0	0
T67	199283	481	0	0
T111	0	2	0	0
T144	0	66	0	0
T150	0	92	0	0
T152	0	148	0	0
T169	0	69	0	0
T170	0	17	0	0
T171	0	5	0	0
T172	0	11	0	0
T173	0	4	0	0
T175	122776	0	0	0
T176	674853	0	0	0
T177	230835	0	0	0
T178	105315	0	0	0
T179	151539	0	0	0
T180	481463	0	0	0
T181	114189	0	0	0
T182	972453	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2683	0	0
T40	716774	0	0	0
T67	199283	361	0	0
T144	0	73	0	0
T150	0	23	0	0
T152	0	181	0	0
T169	0	29	0	0
T170	0	15	0	0
T171	0	2	0	0
T172	0	11	0	0
T173	0	2	0	0
T174	0	4	0	0
T175	122776	0	0	0
T176	674853	0	0	0
T177	230835	0	0	0
T178	105315	0	0	0
T179	151539	0	0	0
T180	481463	0	0	0
T181	114189	0	0	0
T182	972453	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2599	0	0
T40	716774	0	0	0
T67	199283	366	0	0
T144	0	94	0	0
T150	0	33	0	0
T152	0	156	0	0
T169	0	54	0	0
T170	0	17	0	0
T171	0	5	0	0
T172	0	11	0	0
T173	0	12	0	0
T174	0	3	0	0
T175	122776	0	0	0
T176	674853	0	0	0
T177	230835	0	0	0
T178	105315	0	0	0
T179	151539	0	0	0
T180	481463	0	0	0
T181	114189	0	0	0
T182	972453	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2630	0	0
T40	716774	0	0	0
T67	199283	336	0	0
T144	0	68	0	0
T150	0	43	0	0
T152	0	129	0	0
T169	0	59	0	0
T170	0	20	0	0
T171	0	6	0	0
T172	0	5	0	0
T173	0	5	0	0
T174	0	1	0	0
T175	122776	0	0	0
T176	674853	0	0	0
T177	230835	0	0	0
T178	105315	0	0	0
T179	151539	0	0	0
T180	481463	0	0	0
T181	114189	0	0	0
T182	972453	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2572	0	0
T40	716774	0	0	0
T67	199283	365	0	0
T111	0	7	0	0
T144	0	80	0	0
T150	0	62	0	0
T152	0	160	0	0
T169	0	51	0	0
T170	0	20	0	0
T172	0	10	0	0
T173	0	5	0	0
T174	0	7	0	0
T175	122776	0	0	0
T176	674853	0	0	0
T177	230835	0	0	0
T178	105315	0	0	0
T179	151539	0	0	0
T180	481463	0	0	0
T181	114189	0	0	0
T182	972453	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2672	0	0
T40	716774	0	0	0
T67	199283	319	0	0
T144	0	104	0	0
T150	0	59	0	0
T152	0	189	0	0
T169	0	61	0	0
T170	0	16	0	0
T171	0	8	0	0
T172	0	5	0	0
T173	0	12	0	0
T174	0	7	0	0
T175	122776	0	0	0
T176	674853	0	0	0
T177	230835	0	0	0
T178	105315	0	0	0
T179	151539	0	0	0
T180	481463	0	0	0
T181	114189	0	0	0
T182	972453	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2720	0	0
T40	716774	0	0	0
T67	199283	410	0	0
T144	0	70	0	0
T150	0	57	0	0
T152	0	130	0	0
T169	0	50	0	0
T170	0	10	0	0
T171	0	1	0	0
T172	0	10	0	0
T173	0	10	0	0
T174	0	6	0	0
T175	122776	0	0	0
T176	674853	0	0	0
T177	230835	0	0	0
T178	105315	0	0	0
T179	151539	0	0	0
T180	481463	0	0	0
T181	114189	0	0	0
T182	972453	0	0	0