Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
183521 |
1 |
|
|
T1 |
58 |
|
T12 |
652 |
|
T4 |
2673 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
93600 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
67596 |
1 |
|
|
T1 |
57 |
|
T12 |
643 |
|
T4 |
144 |
seven_bytes |
3254 |
1 |
|
|
T4 |
55 |
|
T35 |
70 |
|
T32 |
55 |
six_bytes |
3138 |
1 |
|
|
T4 |
75 |
|
T35 |
73 |
|
T32 |
54 |
five_bytes |
3275 |
1 |
|
|
T4 |
67 |
|
T35 |
69 |
|
T32 |
50 |
four_bytes |
3202 |
1 |
|
|
T4 |
73 |
|
T35 |
71 |
|
T32 |
61 |
three_bytes |
3109 |
1 |
|
|
T4 |
70 |
|
T35 |
77 |
|
T32 |
48 |
two_bytes |
3088 |
1 |
|
|
T4 |
69 |
|
T35 |
73 |
|
T32 |
63 |
one_byte |
3259 |
1 |
|
|
T4 |
63 |
|
T35 |
68 |
|
T32 |
57 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
179993 |
1 |
|
|
T1 |
56 |
|
T12 |
634 |
|
T4 |
2635 |
auto[1] |
3528 |
1 |
|
|
T1 |
2 |
|
T12 |
18 |
|
T4 |
38 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
183521 |
1 |
|
|
T1 |
58 |
|
T12 |
652 |
|
T4 |
2673 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
183505 |
1 |
|
|
T1 |
58 |
|
T12 |
652 |
|
T4 |
2673 |
auto[1] |
16 |
1 |
|
|
T32 |
1 |
|
T29 |
1 |
|
T172 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1253 |
1 |
|
|
T1 |
1 |
|
T12 |
9 |
|
T4 |
6 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3528 |
1 |
|
|
T1 |
2 |
|
T12 |
18 |
|
T4 |
38 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
197024 |
1 |
|
|
T1 |
61 |
|
T12 |
522 |
|
T4 |
4824 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
105293 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
66524 |
1 |
|
|
T1 |
60 |
|
T12 |
514 |
|
T4 |
132 |
seven_bytes |
3565 |
1 |
|
|
T4 |
131 |
|
T35 |
28 |
|
T52 |
13 |
six_bytes |
3637 |
1 |
|
|
T4 |
111 |
|
T35 |
18 |
|
T52 |
12 |
five_bytes |
3577 |
1 |
|
|
T4 |
124 |
|
T35 |
29 |
|
T52 |
10 |
four_bytes |
3617 |
1 |
|
|
T4 |
121 |
|
T35 |
18 |
|
T52 |
8 |
three_bytes |
3621 |
1 |
|
|
T4 |
118 |
|
T35 |
22 |
|
T52 |
7 |
two_bytes |
3553 |
1 |
|
|
T4 |
134 |
|
T35 |
19 |
|
T52 |
9 |
one_byte |
3637 |
1 |
|
|
T4 |
159 |
|
T35 |
25 |
|
T52 |
9 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
193360 |
1 |
|
|
T1 |
59 |
|
T12 |
506 |
|
T4 |
4772 |
auto[1] |
3664 |
1 |
|
|
T1 |
2 |
|
T12 |
16 |
|
T4 |
52 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
197024 |
1 |
|
|
T1 |
61 |
|
T12 |
522 |
|
T4 |
4824 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
197010 |
1 |
|
|
T1 |
61 |
|
T12 |
522 |
|
T4 |
4824 |
auto[1] |
14 |
1 |
|
|
T32 |
2 |
|
T23 |
1 |
|
T144 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1249 |
1 |
|
|
T1 |
1 |
|
T12 |
8 |
|
T4 |
5 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3664 |
1 |
|
|
T1 |
2 |
|
T12 |
16 |
|
T4 |
52 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
369504 |
1 |
|
|
T1 |
111 |
|
T12 |
889 |
|
T4 |
5091 |
auto[1] |
636 |
1 |
|
|
T22 |
93 |
|
T23 |
31 |
|
T25 |
55 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
189741 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
135212 |
1 |
|
|
T1 |
109 |
|
T12 |
875 |
|
T4 |
172 |
seven_bytes |
6420 |
1 |
|
|
T4 |
130 |
|
T35 |
87 |
|
T52 |
19 |
six_bytes |
6496 |
1 |
|
|
T4 |
132 |
|
T35 |
95 |
|
T52 |
18 |
five_bytes |
6528 |
1 |
|
|
T4 |
143 |
|
T35 |
85 |
|
T52 |
10 |
four_bytes |
6539 |
1 |
|
|
T4 |
135 |
|
T35 |
89 |
|
T52 |
18 |
three_bytes |
6478 |
1 |
|
|
T4 |
140 |
|
T35 |
80 |
|
T52 |
24 |
two_bytes |
6336 |
1 |
|
|
T4 |
132 |
|
T35 |
77 |
|
T52 |
11 |
one_byte |
6390 |
1 |
|
|
T4 |
117 |
|
T35 |
73 |
|
T52 |
14 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
362952 |
1 |
|
|
T1 |
107 |
|
T12 |
861 |
|
T4 |
5013 |
auto[1] |
7188 |
1 |
|
|
T1 |
4 |
|
T12 |
28 |
|
T4 |
78 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
370140 |
1 |
|
|
T1 |
111 |
|
T12 |
889 |
|
T4 |
5091 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
370106 |
1 |
|
|
T1 |
111 |
|
T12 |
889 |
|
T4 |
5091 |
auto[1] |
34 |
1 |
|
|
T53 |
1 |
|
T58 |
2 |
|
T143 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2525 |
1 |
|
|
T1 |
2 |
|
T12 |
14 |
|
T4 |
14 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
7188 |
1 |
|
|
T1 |
4 |
|
T12 |
28 |
|
T4 |
78 |