Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

260371528

1

T1

4935

T2

835

T3

414141

full_word

183142183

1

T1

7075

T2

1047

T3

249855

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	443513421	1			T1	12010		T2	1882		T3	663996
auto[TlIntgErrCmd]	109	1			T125	10		T126	2		T127	8
auto[TlIntgErrData]	95	1			T125	7		T126	5		T127	5
auto[TlIntgErrBoth]	86	1			T125	3		T126	3		T127	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

229294700

1

T1

7773

T2

859

T3

334381

auto[1]

214219011

1

T1

4237

T2

1023

T3

329615

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrData]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	157959928	1			T1	3194		T2	515		T3	244738
auto[TlIntgErrNone]	partial	auto[1]	102411326	1			T1	1741		T2	320		T3	169403
auto[TlIntgErrNone]	full_word	auto[0]	71334635	1			T1	4579		T2	344		T3	89643
auto[TlIntgErrNone]	full_word	auto[1]	111807532	1			T1	2496		T2	703		T3	160212
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T125	4		T126	1		T127	3
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T125	5		T126	1		T127	5
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T173	1		T174	1		T175	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T125	1		T176	1		T174	1
auto[TlIntgErrData]	partial	auto[0]	52	1			T125	4		T126	3		T127	3
auto[TlIntgErrData]	partial	auto[1]	39	1			T125	3		T126	2		T127	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T177	1		T178	1		T179	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T125	1		T126	1		T127	4
auto[TlIntgErrBoth]	partial	auto[1]	45	1			T125	2		T126	2		T127	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T176	1		T180	1		T179	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T178	1		-	-		-	-