Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	725706	0	0
entropy_period_rd_A	2147483647	2356	0	0
intr_enable_rd_A	2147483647	3155	0	0
prefix_0_rd_A	2147483647	2411	0	0
prefix_10_rd_A	2147483647	2444	0	0
prefix_1_rd_A	2147483647	2375	0	0
prefix_2_rd_A	2147483647	2452	0	0
prefix_3_rd_A	2147483647	2558	0	0
prefix_4_rd_A	2147483647	2414	0	0
prefix_5_rd_A	2147483647	2414	0	0
prefix_6_rd_A	2147483647	2472	0	0
prefix_7_rd_A	2147483647	2446	0	0
prefix_8_rd_A	2147483647	2538	0	0
prefix_9_rd_A	2147483647	2523	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	725706	0	0
T4	338452	16934	0	0
T5	465389	0	0	0
T15	81118	0	0	0
T21	3047	0	0	0
T22	275613	0	0	0
T26	1976	0	0	0
T30	0	70953	0	0
T51	639367	0	0	0
T75	9982	0	0	0
T76	0	25497	0	0
T77	0	34569	0	0
T79	0	19185	0	0
T83	614581	0	0	0
T84	406957	0	0	0
T131	0	52584	0	0
T132	0	86478	0	0
T133	0	58177	0	0
T134	0	198070	0	0
T135	0	64265	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2356	0	0
T77	358520	67	0	0
T91	0	30	0	0
T92	0	10	0	0
T94	0	15	0	0
T106	0	43	0	0
T146	0	31	0	0
T147	0	11	0	0
T148	0	224	0	0
T149	0	210	0	0
T150	0	1	0	0
T151	1091	0	0	0
T152	553881	0	0	0
T153	474216	0	0	0
T154	646563	0	0	0
T155	255142	0	0	0
T156	132816	0	0	0
T157	15814	0	0	0
T158	942974	0	0	0
T159	437906	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3155	0	0
T77	358520	42	0	0
T91	0	35	0	0
T106	0	62	0	0
T130	0	6	0	0
T146	0	29	0	0
T147	0	7	0	0
T148	0	457	0	0
T151	1091	0	0	0
T152	553881	0	0	0
T153	474216	0	0	0
T154	646563	0	0	0
T155	255142	0	0	0
T156	132816	0	0	0
T157	15814	0	0	0
T158	942974	0	0	0
T159	437906	0	0	0
T160	0	13	0	0
T161	0	7	0	0
T162	0	18	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2411	0	0
T77	358520	48	0	0
T91	0	30	0	0
T92	0	9	0	0
T94	0	18	0	0
T106	0	23	0	0
T146	0	32	0	0
T147	0	5	0	0
T148	0	469	0	0
T149	0	253	0	0
T151	1091	0	0	0
T152	553881	0	0	0
T153	474216	0	0	0
T154	646563	0	0	0
T155	255142	0	0	0
T156	132816	0	0	0
T157	15814	0	0	0
T158	942974	0	0	0
T159	437906	0	0	0
T160	0	15	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2444	0	0
T77	358520	67	0	0
T91	0	48	0	0
T94	0	30	0	0
T106	0	16	0	0
T146	0	39	0	0
T147	0	12	0	0
T148	0	473	0	0
T149	0	250	0	0
T151	1091	0	0	0
T152	553881	0	0	0
T153	474216	0	0	0
T154	646563	0	0	0
T155	255142	0	0	0
T156	132816	0	0	0
T157	15814	0	0	0
T158	942974	0	0	0
T159	437906	0	0	0
T160	0	8	0	0
T163	0	5	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2375	0	0
T77	358520	41	0	0
T91	0	26	0	0
T92	0	6	0	0
T94	0	20	0	0
T106	0	21	0	0
T146	0	63	0	0
T147	0	7	0	0
T148	0	413	0	0
T149	0	196	0	0
T150	0	3	0	0
T151	1091	0	0	0
T152	553881	0	0	0
T153	474216	0	0	0
T154	646563	0	0	0
T155	255142	0	0	0
T156	132816	0	0	0
T157	15814	0	0	0
T158	942974	0	0	0
T159	437906	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2452	0	0
T77	358520	45	0	0
T91	0	45	0	0
T92	0	5	0	0
T94	0	16	0	0
T106	0	21	0	0
T146	0	12	0	0
T147	0	6	0	0
T148	0	481	0	0
T149	0	211	0	0
T150	0	2	0	0
T151	1091	0	0	0
T152	553881	0	0	0
T153	474216	0	0	0
T154	646563	0	0	0
T155	255142	0	0	0
T156	132816	0	0	0
T157	15814	0	0	0
T158	942974	0	0	0
T159	437906	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2558	0	0
T77	358520	79	0	0
T91	0	45	0	0
T92	0	10	0	0
T94	0	7	0	0
T106	0	19	0	0
T146	0	27	0	0
T147	0	2	0	0
T148	0	478	0	0
T149	0	249	0	0
T151	1091	0	0	0
T152	553881	0	0	0
T153	474216	0	0	0
T154	646563	0	0	0
T155	255142	0	0	0
T156	132816	0	0	0
T157	15814	0	0	0
T158	942974	0	0	0
T159	437906	0	0	0
T160	0	3	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2414	0	0
T77	358520	63	0	0
T91	0	18	0	0
T92	0	9	0	0
T106	0	33	0	0
T146	0	39	0	0
T147	0	12	0	0
T148	0	441	0	0
T149	0	202	0	0
T150	0	2	0	0
T151	1091	0	0	0
T152	553881	0	0	0
T153	474216	0	0	0
T154	646563	0	0	0
T155	255142	0	0	0
T156	132816	0	0	0
T157	15814	0	0	0
T158	942974	0	0	0
T159	437906	0	0	0
T164	0	3	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2414	0	0
T77	358520	17	0	0
T91	0	27	0	0
T92	0	8	0	0
T106	0	28	0	0
T146	0	27	0	0
T147	0	15	0	0
T148	0	433	0	0
T149	0	204	0	0
T150	0	9	0	0
T151	1091	0	0	0
T152	553881	0	0	0
T153	474216	0	0	0
T154	646563	0	0	0
T155	255142	0	0	0
T156	132816	0	0	0
T157	15814	0	0	0
T158	942974	0	0	0
T159	437906	0	0	0
T160	0	14	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2472	0	0
T77	358520	28	0	0
T91	0	20	0	0
T92	0	3	0	0
T106	0	21	0	0
T146	0	27	0	0
T147	0	11	0	0
T148	0	474	0	0
T149	0	211	0	0
T151	1091	0	0	0
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T153	474216	0	0	0
T154	646563	0	0	0
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T156	132816	0	0	0
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T158	942974	0	0	0
T159	437906	0	0	0
T160	0	5	0	0
T164	0	1	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2446	0	0
T77	358520	56	0	0
T91	0	37	0	0
T92	0	9	0	0
T106	0	14	0	0
T146	0	66	0	0
T147	0	9	0	0
T148	0	496	0	0
T149	0	266	0	0
T150	0	3	0	0
T151	1091	0	0	0
T152	553881	0	0	0
T153	474216	0	0	0
T154	646563	0	0	0
T155	255142	0	0	0
T156	132816	0	0	0
T157	15814	0	0	0
T158	942974	0	0	0
T159	437906	0	0	0
T160	0	6	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2538	0	0
T77	358520	49	0	0
T91	0	30	0	0
T92	0	9	0	0
T106	0	23	0	0
T146	0	65	0	0
T147	0	9	0	0
T148	0	450	0	0
T149	0	241	0	0
T150	0	3	0	0
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T153	474216	0	0	0
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T157	15814	0	0	0
T158	942974	0	0	0
T159	437906	0	0	0
T160	0	4	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2523	0	0
T77	358520	67	0	0
T91	0	34	0	0
T92	0	11	0	0
T106	0	24	0	0
T146	0	41	0	0
T147	0	9	0	0
T148	0	442	0	0
T149	0	261	0	0
T150	0	3	0	0
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T152	553881	0	0	0
T153	474216	0	0	0
T154	646563	0	0	0
T155	255142	0	0	0
T156	132816	0	0	0
T157	15814	0	0	0
T158	942974	0	0	0
T159	437906	0	0	0
T160	0	3	0	0