Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 259158737 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 185656080 1 T1 344643 T2 22470 T3 1048



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 229727658 1 T1 455801 T2 15563 T3 681
values[0x0] 103328316 1 T1 218696 T2 5855 T3 459
values[0x1] 111758843 1 T1 237341 T2 5961 T3 486



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 201462516 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 243352301 1 T1 470018 T2 23760 T3 1167



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 1364313 1 T1 3348 T2 92 T3 7
valid_sources[0x01] 1342541 1 T1 3560 T2 96 T3 3
valid_sources[0x02] 1359890 1 T1 3402 T2 111 T3 6
valid_sources[0x03] 1344218 1 T1 3715 T2 96 T3 8
valid_sources[0x04] 1337949 1 T1 3642 T2 97 T3 9
valid_sources[0x05] 1998876 1 T1 3403 T2 80 T3 4
valid_sources[0x06] 1346620 1 T1 3424 T2 79 T3 1
valid_sources[0x07] 1347726 1 T1 3497 T2 111 T3 2
valid_sources[0x08] 1343186 1 T1 3311 T2 87 T3 2
valid_sources[0x09] 1362204 1 T1 4054 T2 125 T3 6
valid_sources[0x0a] 2214285 1 T1 3637 T2 138 T3 4
valid_sources[0x0b] 1343641 1 T1 3537 T2 105 T3 15
valid_sources[0x0c] 1362514 1 T1 3625 T2 129 T3 8
valid_sources[0x0d] 1342557 1 T1 3702 T2 105 T3 8
valid_sources[0x0e] 1350792 1 T1 3662 T2 90 T3 3
valid_sources[0x0f] 3943159 1 T1 3731 T2 116 T3 11
valid_sources[0x10] 1338094 1 T1 3532 T2 108 T3 4
valid_sources[0x11] 1351550 1 T1 3590 T2 90 T3 14
valid_sources[0x12] 1358286 1 T1 3615 T2 105 T3 11
valid_sources[0x13] 1343104 1 T1 3655 T2 95 T3 8
valid_sources[0x14] 3731510 1 T1 3607 T2 106 T3 5
valid_sources[0x15] 1343490 1 T1 3693 T2 92 T3 5
valid_sources[0x16] 1340515 1 T1 3668 T2 112 T3 7
valid_sources[0x17] 1484134 1 T1 3451 T2 99 T5 16
valid_sources[0x18] 1404015 1 T1 3550 T2 126 T3 3
valid_sources[0x19] 1352565 1 T1 3455 T2 102 T3 6
valid_sources[0x1a] 4546226 1 T1 3541 T2 103 T3 7
valid_sources[0x1b] 6544597 1 T1 3436 T2 88 T3 4
valid_sources[0x1c] 1346221 1 T1 3467 T2 129 T3 7
valid_sources[0x1d] 1807106 1 T1 3733 T2 113 T3 10
valid_sources[0x1e] 1345090 1 T1 3569 T2 109 T3 12
valid_sources[0x1f] 1337843 1 T1 3634 T2 113 T3 3
valid_sources[0x20] 1334755 1 T1 3587 T2 99 T3 7
valid_sources[0x21] 1341201 1 T1 3712 T2 117 T3 8
valid_sources[0x22] 1339345 1 T1 3517 T2 110 T3 6
valid_sources[0x23] 4359701 1 T1 3284 T2 102 T3 4
valid_sources[0x24] 2243294 1 T1 3663 T2 107 T3 7
valid_sources[0x25] 1337682 1 T1 3535 T2 113 T3 6
valid_sources[0x26] 1345715 1 T1 3782 T2 102 T3 11
valid_sources[0x27] 3326038 1 T1 3451 T2 113 T3 12
valid_sources[0x28] 1343721 1 T1 3537 T2 120 T3 11
valid_sources[0x29] 1420492 1 T1 3422 T2 78 T3 4
valid_sources[0x2a] 1367439 1 T1 3648 T2 100 T3 5
valid_sources[0x2b] 1344431 1 T1 3502 T2 95 T3 4
valid_sources[0x2c] 4354116 1 T1 3518 T2 107 T3 11
valid_sources[0x2d] 1346986 1 T1 3697 T2 123 T3 6
valid_sources[0x2e] 1406579 1 T1 3732 T2 110 T3 9
valid_sources[0x2f] 3348447 1 T1 3575 T2 133 T3 6
valid_sources[0x30] 1347602 1 T1 3636 T2 117 T3 5
valid_sources[0x31] 1344564 1 T1 3679 T2 91 T3 1
valid_sources[0x32] 1500904 1 T1 3384 T2 112 T3 5
valid_sources[0x33] 1350357 1 T1 3534 T2 114 T3 8
valid_sources[0x34] 1346842 1 T1 3501 T2 100 T3 6
valid_sources[0x35] 6575498 1 T1 3589 T2 97 T3 6
valid_sources[0x36] 1345618 1 T1 3533 T2 149 T3 8
valid_sources[0x37] 2201561 1 T1 3580 T2 107 T3 7
valid_sources[0x38] 1368054 1 T1 3607 T2 105 T4 2
valid_sources[0x39] 1346462 1 T1 3310 T2 74 T3 2
valid_sources[0x3a] 1343967 1 T1 3471 T2 102 T3 7
valid_sources[0x3b] 3683267 1 T1 3537 T2 98 T3 3
valid_sources[0x3c] 1343977 1 T1 3578 T2 108 T3 9
valid_sources[0x3d] 3310240 1 T1 3574 T2 95 T3 8
valid_sources[0x3e] 3292674 1 T1 3272 T2 101 T3 7
valid_sources[0x3f] 1374038 1 T1 3507 T2 97 T3 8
valid_sources[0x40] 1348480 1 T1 3350 T2 136 T3 9
valid_sources[0x41] 1358228 1 T1 3632 T2 102 T3 3
valid_sources[0x42] 1344694 1 T1 3564 T2 90 T3 2
valid_sources[0x43] 1339906 1 T1 3562 T2 115 T3 9
valid_sources[0x44] 1461853 1 T1 3593 T2 106 T3 9
valid_sources[0x45] 2263337 1 T1 3574 T2 92 T3 6
valid_sources[0x46] 1401258 1 T1 3697 T2 118 T3 5
valid_sources[0x47] 1338688 1 T1 3503 T2 118 T3 5
valid_sources[0x48] 1343035 1 T1 3492 T2 119 T3 5
valid_sources[0x49] 1341705 1 T1 3672 T2 114 T3 2
valid_sources[0x4a] 3332966 1 T1 3619 T2 104 T4 7
valid_sources[0x4b] 1437030 1 T1 3766 T2 121 T3 8
valid_sources[0x4c] 1346932 1 T1 3642 T2 115 T3 3
valid_sources[0x4d] 1439757 1 T1 3477 T2 85 T3 10
valid_sources[0x4e] 1338164 1 T1 3684 T2 133 T3 6
valid_sources[0x4f] 2904132 1 T1 3446 T2 108 T3 5
valid_sources[0x50] 1364992 1 T1 3479 T2 85 T3 6
valid_sources[0x51] 1493755 1 T1 3592 T2 79 T3 9
valid_sources[0x52] 1353115 1 T1 3446 T2 118 T3 9
valid_sources[0x53] 1341194 1 T1 3426 T2 149 T3 3
valid_sources[0x54] 1345114 1 T1 3587 T2 111 T3 6
valid_sources[0x55] 1987686 1 T1 3375 T2 124 T3 17
valid_sources[0x56] 1345011 1 T1 3705 T2 112 T3 4
valid_sources[0x57] 1338281 1 T1 3671 T2 103 T3 6
valid_sources[0x58] 1404357 1 T1 3621 T2 113 T3 5
valid_sources[0x59] 1346922 1 T1 3502 T2 127 T3 4
valid_sources[0x5a] 1483264 1 T1 3676 T2 78 T3 7
valid_sources[0x5b] 2022929 1 T1 3609 T2 129 T3 16
valid_sources[0x5c] 1530094 1 T1 3408 T2 155 T3 10
valid_sources[0x5d] 1345177 1 T1 3760 T2 141 T3 6
valid_sources[0x5e] 1351433 1 T1 3668 T2 96 T3 5
valid_sources[0x5f] 1825823 1 T1 3292 T2 119 T3 5
valid_sources[0x60] 3656311 1 T1 3727 T2 137 T3 8
valid_sources[0x61] 1345793 1 T1 3604 T2 133 T3 6
valid_sources[0x62] 1938942 1 T1 3722 T2 90 T3 9
valid_sources[0x63] 1373711 1 T1 3578 T2 140 T3 4
valid_sources[0x64] 1549389 1 T1 3386 T2 96 T3 4
valid_sources[0x65] 2195902 1 T1 3709 T2 125 T3 11
valid_sources[0x66] 3302267 1 T1 3471 T2 117 T3 1
valid_sources[0x67] 2345247 1 T1 3623 T2 105 T3 6
valid_sources[0x68] 1346876 1 T1 3454 T2 108 T3 3
valid_sources[0x69] 1345828 1 T1 3666 T2 100 T3 9
valid_sources[0x6a] 1337053 1 T1 3610 T2 120 T3 6
valid_sources[0x6b] 1340669 1 T1 3745 T2 99 T3 5
valid_sources[0x6c] 2283039 1 T1 3714 T2 82 T3 7
valid_sources[0x6d] 1482596 1 T1 3494 T2 105 T3 7
valid_sources[0x6e] 1343612 1 T1 3577 T2 102 T3 3
valid_sources[0x6f] 2409050 1 T1 3746 T2 102 T3 1
valid_sources[0x70] 1341064 1 T1 3745 T2 109 T3 5
valid_sources[0x71] 1342793 1 T1 3687 T2 92 T3 9
valid_sources[0x72] 2050232 1 T1 3564 T2 98 T3 7
valid_sources[0x73] 1343693 1 T1 3696 T2 118 T3 7
valid_sources[0x74] 1368526 1 T1 3588 T2 77 T3 7
valid_sources[0x75] 1341740 1 T1 3673 T2 121 T3 4
valid_sources[0x76] 1343116 1 T1 3469 T2 88 T3 5
valid_sources[0x77] 1339032 1 T1 3613 T2 73 T3 7
valid_sources[0x78] 1340732 1 T1 3543 T2 79 T3 6
valid_sources[0x79] 1345705 1 T1 3388 T2 101 T3 5
valid_sources[0x7a] 1348947 1 T1 3686 T2 100 T3 8
valid_sources[0x7b] 1345046 1 T1 3482 T2 99 T3 11
valid_sources[0x7c] 1339854 1 T1 3407 T2 86 T3 10
valid_sources[0x7d] 2434886 1 T1 3595 T2 111 T3 4
valid_sources[0x7e] 1343257 1 T1 3520 T2 115 T3 5
valid_sources[0x7f] 1340893 1 T1 3440 T2 113 T3 8
valid_sources[0x80] 2202230 1 T1 3688 T2 94 T3 4



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 71765152 1 T1 118133 T2 12776 T3 327
values[0x0] all_enables biggest_size 61177120 1 T1 123190 T2 4926 T3 353
values[0x1] all_enables biggest_size 52713808 1 T1 103320 T2 4768 T3 368

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%