Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

262849961

1

T1

567195

T2

4909

T3

578

full_word

185887702

1

T1

344643

T2

22470

T3

1048

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	448737403	1			T1	911838		T2	27379		T3	1626
auto[TlIntgErrCmd]	87	1			T128	3		T129	4		T130	6
auto[TlIntgErrData]	87	1			T128	2		T129	5		T130	4
auto[TlIntgErrBoth]	86	1			T128	5		T129	1		T130	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

230455967

1

T1

455801

T2

15563

T3

681

auto[1]

218281696

1

T1

456037

T2

11816

T3

945

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	158631926	1			T1	337668		T2	2787		T3	354
auto[TlIntgErrNone]	partial	auto[1]	104217800	1			T1	229527		T2	2122		T3	224
auto[TlIntgErrNone]	full_word	auto[0]	71823934	1			T1	118133		T2	12776		T3	327
auto[TlIntgErrNone]	full_word	auto[1]	114063743	1			T1	226510		T2	9694		T3	721
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T128	3		T129	1		T130	3
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T129	3		T130	3		T183	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T187	1		T188	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T185	1		T189	2		T190	1
auto[TlIntgErrData]	partial	auto[0]	33	1			T128	2		T130	1		T191	1
auto[TlIntgErrData]	partial	auto[1]	46	1			T129	4		T130	3		T183	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T192	1		T186	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1			T129	1		T184	1		T193	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T128	1		T130	4		T183	1
auto[TlIntgErrBoth]	partial	auto[1]	41	1			T128	3		T129	1		T130	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T130	2		T192	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T128	1		T130	1		T187	1