Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	863214	0	0
entropy_period_rd_A	2147483647	1845	0	0
intr_enable_rd_A	2147483647	2352	0	0
prefix_0_rd_A	2147483647	1405	0	0
prefix_10_rd_A	2147483647	1462	0	0
prefix_1_rd_A	2147483647	1638	0	0
prefix_2_rd_A	2147483647	1488	0	0
prefix_3_rd_A	2147483647	1449	0	0
prefix_4_rd_A	2147483647	1506	0	0
prefix_5_rd_A	2147483647	1475	0	0
prefix_6_rd_A	2147483647	1515	0	0
prefix_7_rd_A	2147483647	1513	0	0
prefix_8_rd_A	2147483647	1369	0	0
prefix_9_rd_A	2147483647	1482	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	863214	0	0
T21	53245	0	0	0
T32	457916	68118	0	0
T45	115077	0	0	0
T59	0	69276	0	0
T64	0	15941	0	0
T68	3071	0	0	0
T69	124744	0	0	0
T89	0	30253	0	0
T90	0	37088	0	0
T91	0	15110	0	0
T111	935	0	0	0
T113	55584	0	0	0
T134	0	58721	0	0
T135	0	73325	0	0
T136	0	52297	0	0
T137	0	55698	0	0
T138	135494	0	0	0
T139	45996	0	0	0
T140	199241	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1845	0	0
T89	445020	94	0	0
T90	0	84	0	0
T91	0	52	0	0
T96	0	20	0	0
T99	0	6	0	0
T128	0	92	0	0
T130	0	73	0	0
T156	0	98	0	0
T157	0	4	0	0
T158	0	4	0	0
T159	199872	0	0	0
T160	948191	0	0	0
T161	662681	0	0	0
T162	919	0	0	0
T163	126061	0	0	0
T164	14363	0	0	0
T165	179521	0	0	0
T166	663721	0	0	0
T167	85108	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2352	0	0
T89	445020	58	0	0
T90	0	85	0	0
T91	0	74	0	0
T96	0	9	0	0
T128	0	63	0	0
T130	0	76	0	0
T133	0	26	0	0
T156	0	113	0	0
T157	0	15	0	0
T159	199872	0	0	0
T160	948191	0	0	0
T161	662681	0	0	0
T162	919	0	0	0
T163	126061	0	0	0
T164	14363	0	0	0
T165	179521	0	0	0
T166	663721	0	0	0
T167	85108	0	0	0
T168	0	8	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1405	0	0
T89	445020	68	0	0
T90	0	82	0	0
T91	0	38	0	0
T96	0	19	0	0
T101	0	44	0	0
T128	0	38	0	0
T130	0	54	0	0
T156	0	85	0	0
T157	0	1	0	0
T158	0	3	0	0
T159	199872	0	0	0
T160	948191	0	0	0
T161	662681	0	0	0
T162	919	0	0	0
T163	126061	0	0	0
T164	14363	0	0	0
T165	179521	0	0	0
T166	663721	0	0	0
T167	85108	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1462	0	0
T89	445020	88	0	0
T90	0	98	0	0
T91	0	49	0	0
T96	0	20	0	0
T99	0	8	0	0
T128	0	30	0	0
T130	0	51	0	0
T156	0	137	0	0
T157	0	2	0	0
T158	0	6	0	0
T159	199872	0	0	0
T160	948191	0	0	0
T161	662681	0	0	0
T162	919	0	0	0
T163	126061	0	0	0
T164	14363	0	0	0
T165	179521	0	0	0
T166	663721	0	0	0
T167	85108	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1638	0	0
T89	445020	87	0	0
T90	0	111	0	0
T91	0	48	0	0
T96	0	20	0	0
T99	0	12	0	0
T128	0	41	0	0
T130	0	55	0	0
T156	0	127	0	0
T157	0	13	0	0
T158	0	8	0	0
T159	199872	0	0	0
T160	948191	0	0	0
T161	662681	0	0	0
T162	919	0	0	0
T163	126061	0	0	0
T164	14363	0	0	0
T165	179521	0	0	0
T166	663721	0	0	0
T167	85108	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1488	0	0
T89	445020	86	0	0
T90	0	150	0	0
T91	0	59	0	0
T96	0	12	0	0
T99	0	1	0	0
T128	0	58	0	0
T130	0	18	0	0
T156	0	67	0	0
T157	0	12	0	0
T158	0	5	0	0
T159	199872	0	0	0
T160	948191	0	0	0
T161	662681	0	0	0
T162	919	0	0	0
T163	126061	0	0	0
T164	14363	0	0	0
T165	179521	0	0	0
T166	663721	0	0	0
T167	85108	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1449	0	0
T89	445020	98	0	0
T90	0	104	0	0
T91	0	39	0	0
T96	0	18	0	0
T99	0	2	0	0
T128	0	26	0	0
T130	0	64	0	0
T156	0	90	0	0
T157	0	6	0	0
T158	0	3	0	0
T159	199872	0	0	0
T160	948191	0	0	0
T161	662681	0	0	0
T162	919	0	0	0
T163	126061	0	0	0
T164	14363	0	0	0
T165	179521	0	0	0
T166	663721	0	0	0
T167	85108	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1506	0	0
T89	445020	86	0	0
T90	0	134	0	0
T91	0	42	0	0
T96	0	6	0	0
T101	0	35	0	0
T128	0	41	0	0
T130	0	51	0	0
T156	0	89	0	0
T157	0	12	0	0
T158	0	11	0	0
T159	199872	0	0	0
T160	948191	0	0	0
T161	662681	0	0	0
T162	919	0	0	0
T163	126061	0	0	0
T164	14363	0	0	0
T165	179521	0	0	0
T166	663721	0	0	0
T167	85108	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1475	0	0
T89	445020	87	0	0
T90	0	88	0	0
T91	0	56	0	0
T96	0	21	0	0
T99	0	14	0	0
T128	0	26	0	0
T130	0	65	0	0
T156	0	119	0	0
T157	0	9	0	0
T158	0	6	0	0
T159	199872	0	0	0
T160	948191	0	0	0
T161	662681	0	0	0
T162	919	0	0	0
T163	126061	0	0	0
T164	14363	0	0	0
T165	179521	0	0	0
T166	663721	0	0	0
T167	85108	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1515	0	0
T89	445020	31	0	0
T90	0	120	0	0
T91	0	40	0	0
T96	0	7	0	0
T99	0	11	0	0
T128	0	53	0	0
T130	0	48	0	0
T156	0	115	0	0
T157	0	12	0	0
T158	0	12	0	0
T159	199872	0	0	0
T160	948191	0	0	0
T161	662681	0	0	0
T162	919	0	0	0
T163	126061	0	0	0
T164	14363	0	0	0
T165	179521	0	0	0
T166	663721	0	0	0
T167	85108	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1513	0	0
T89	445020	80	0	0
T90	0	79	0	0
T91	0	33	0	0
T96	0	12	0	0
T101	0	55	0	0
T128	0	38	0	0
T130	0	45	0	0
T156	0	138	0	0
T157	0	13	0	0
T158	0	1	0	0
T159	199872	0	0	0
T160	948191	0	0	0
T161	662681	0	0	0
T162	919	0	0	0
T163	126061	0	0	0
T164	14363	0	0	0
T165	179521	0	0	0
T166	663721	0	0	0
T167	85108	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1369	0	0
T89	445020	79	0	0
T90	0	77	0	0
T91	0	12	0	0
T96	0	7	0	0
T99	0	3	0	0
T128	0	28	0	0
T130	0	27	0	0
T156	0	88	0	0
T157	0	9	0	0
T158	0	7	0	0
T159	199872	0	0	0
T160	948191	0	0	0
T161	662681	0	0	0
T162	919	0	0	0
T163	126061	0	0	0
T164	14363	0	0	0
T165	179521	0	0	0
T166	663721	0	0	0
T167	85108	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1482	0	0
T89	445020	101	0	0
T90	0	95	0	0
T91	0	40	0	0
T96	0	10	0	0
T99	0	15	0	0
T128	0	37	0	0
T130	0	40	0	0
T156	0	89	0	0
T157	0	6	0	0
T158	0	7	0	0
T159	199872	0	0	0
T160	948191	0	0	0
T161	662681	0	0	0
T162	919	0	0	0
T163	126061	0	0	0
T164	14363	0	0	0
T165	179521	0	0	0
T166	663721	0	0	0
T167	85108	0	0	0