Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
160524 |
1 |
|
|
T4 |
2073 |
|
T7 |
1239 |
|
T10 |
583 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
81577 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
59679 |
1 |
|
|
T4 |
63 |
|
T7 |
33 |
|
T10 |
573 |
seven_bytes |
2805 |
1 |
|
|
T4 |
67 |
|
T7 |
41 |
|
T61 |
40 |
six_bytes |
2683 |
1 |
|
|
T4 |
53 |
|
T7 |
37 |
|
T61 |
28 |
five_bytes |
2740 |
1 |
|
|
T4 |
56 |
|
T7 |
31 |
|
T61 |
31 |
four_bytes |
2743 |
1 |
|
|
T4 |
68 |
|
T7 |
33 |
|
T61 |
24 |
three_bytes |
2772 |
1 |
|
|
T4 |
49 |
|
T7 |
45 |
|
T61 |
36 |
two_bytes |
2786 |
1 |
|
|
T4 |
48 |
|
T7 |
34 |
|
T61 |
25 |
one_byte |
2739 |
1 |
|
|
T4 |
49 |
|
T7 |
31 |
|
T61 |
33 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
157246 |
1 |
|
|
T4 |
2051 |
|
T7 |
1223 |
|
T10 |
563 |
auto[1] |
3278 |
1 |
|
|
T4 |
22 |
|
T7 |
16 |
|
T10 |
20 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
160524 |
1 |
|
|
T4 |
2073 |
|
T7 |
1239 |
|
T10 |
583 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
160513 |
1 |
|
|
T4 |
2073 |
|
T7 |
1239 |
|
T10 |
583 |
auto[1] |
11 |
1 |
|
|
T57 |
2 |
|
T167 |
1 |
|
T168 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1130 |
1 |
|
|
T4 |
2 |
|
T7 |
1 |
|
T10 |
10 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3278 |
1 |
|
|
T4 |
22 |
|
T7 |
16 |
|
T10 |
20 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
167132 |
1 |
|
|
T4 |
969 |
|
T7 |
1577 |
|
T10 |
696 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
83997 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
63497 |
1 |
|
|
T4 |
21 |
|
T7 |
47 |
|
T10 |
682 |
seven_bytes |
2895 |
1 |
|
|
T4 |
31 |
|
T7 |
44 |
|
T61 |
20 |
six_bytes |
2737 |
1 |
|
|
T4 |
25 |
|
T7 |
44 |
|
T61 |
29 |
five_bytes |
2762 |
1 |
|
|
T4 |
25 |
|
T7 |
47 |
|
T61 |
22 |
four_bytes |
2792 |
1 |
|
|
T4 |
31 |
|
T7 |
42 |
|
T61 |
25 |
three_bytes |
2890 |
1 |
|
|
T4 |
26 |
|
T7 |
43 |
|
T61 |
22 |
two_bytes |
2831 |
1 |
|
|
T4 |
19 |
|
T7 |
38 |
|
T61 |
32 |
one_byte |
2731 |
1 |
|
|
T4 |
16 |
|
T7 |
40 |
|
T61 |
25 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
163729 |
1 |
|
|
T4 |
949 |
|
T7 |
1561 |
|
T10 |
668 |
auto[1] |
3403 |
1 |
|
|
T4 |
20 |
|
T7 |
16 |
|
T10 |
28 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
167132 |
1 |
|
|
T4 |
969 |
|
T7 |
1577 |
|
T10 |
696 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
167124 |
1 |
|
|
T4 |
969 |
|
T7 |
1577 |
|
T10 |
696 |
auto[1] |
8 |
1 |
|
|
T169 |
1 |
|
T45 |
1 |
|
T46 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1219 |
1 |
|
|
T4 |
1 |
|
T7 |
2 |
|
T10 |
14 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3403 |
1 |
|
|
T4 |
20 |
|
T7 |
16 |
|
T10 |
28 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
334069 |
1 |
|
|
T4 |
1685 |
|
T7 |
2693 |
|
T10 |
1662 |
auto[1] |
520 |
1 |
|
|
T54 |
106 |
|
T56 |
55 |
|
T57 |
43 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
167908 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
127406 |
1 |
|
|
T4 |
54 |
|
T7 |
76 |
|
T10 |
1640 |
seven_bytes |
5682 |
1 |
|
|
T4 |
45 |
|
T7 |
82 |
|
T61 |
62 |
six_bytes |
5614 |
1 |
|
|
T4 |
55 |
|
T7 |
72 |
|
T61 |
73 |
five_bytes |
5578 |
1 |
|
|
T4 |
51 |
|
T7 |
76 |
|
T61 |
63 |
four_bytes |
5528 |
1 |
|
|
T4 |
52 |
|
T7 |
59 |
|
T61 |
63 |
three_bytes |
5663 |
1 |
|
|
T4 |
54 |
|
T7 |
61 |
|
T61 |
61 |
two_bytes |
5651 |
1 |
|
|
T4 |
50 |
|
T7 |
64 |
|
T61 |
92 |
one_byte |
5559 |
1 |
|
|
T4 |
32 |
|
T7 |
79 |
|
T61 |
81 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
327971 |
1 |
|
|
T4 |
1667 |
|
T7 |
2661 |
|
T10 |
1618 |
auto[1] |
6618 |
1 |
|
|
T4 |
18 |
|
T7 |
32 |
|
T10 |
44 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
334589 |
1 |
|
|
T4 |
1685 |
|
T7 |
2693 |
|
T10 |
1662 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
334565 |
1 |
|
|
T4 |
1685 |
|
T7 |
2693 |
|
T10 |
1662 |
auto[1] |
24 |
1 |
|
|
T48 |
1 |
|
T54 |
1 |
|
T39 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2347 |
1 |
|
|
T4 |
2 |
|
T7 |
6 |
|
T10 |
22 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6618 |
1 |
|
|
T4 |
18 |
|
T7 |
32 |
|
T10 |
44 |