Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	255880873	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

183527383

1

T1

912061

T2

1103

T3

323719

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	227209946	1			T1	117692		T2	843		T3	437353
values[0x0]	101925273	1			T1	548310		T2	511		T3	207097
values[0x1]	110273037	1			T1	594328		T2	554		T3	227522

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	198797038	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

240611218

1

T1

122110

T2

1292

T3

446180

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1366358	1			T1	9038		T2	18		T3	3646
valid_sources[0x01]	1769125	1			T1	9359		T2	16		T3	3112
valid_sources[0x02]	1378244	1			T1	9079		T2	27		T3	3496
valid_sources[0x03]	1354930	1			T1	9047		T3	3332		T11	1
valid_sources[0x04]	1358861	1			T1	8975		T2	18		T3	3653
valid_sources[0x05]	1996368	1			T1	9591		T3	4290		T12	3432
valid_sources[0x06]	1356289	1			T1	9118		T2	22		T3	3026
valid_sources[0x07]	1372863	1			T1	8734		T3	3400		T12	3399
valid_sources[0x08]	2002978	1			T1	9038		T3	3702		T12	3304
valid_sources[0x09]	1361484	1			T1	9093		T3	4963		T12	3259
valid_sources[0x0a]	1356697	1			T1	9240		T3	3422		T12	3299
valid_sources[0x0b]	1691284	1			T1	9352		T2	32		T3	3636
valid_sources[0x0c]	1408159	1			T1	8885		T3	3044		T12	3353
valid_sources[0x0d]	1356580	1			T1	8990		T2	13		T3	4309
valid_sources[0x0e]	1357101	1			T1	8903		T2	15		T3	3480
valid_sources[0x0f]	1351468	1			T1	9165		T2	19		T3	2546
valid_sources[0x10]	1355444	1			T1	8996		T2	18		T3	3537
valid_sources[0x11]	1352191	1			T1	9268		T2	1		T3	3091
valid_sources[0x12]	3465353	1			T1	8946		T3	2891		T11	2
valid_sources[0x13]	1358794	1			T1	9345		T2	9		T3	3719
valid_sources[0x14]	1357130	1			T1	9123		T3	4040		T11	3
valid_sources[0x15]	1403854	1			T1	8964		T3	3836		T12	3230
valid_sources[0x16]	2191815	1			T1	9217		T3	3023		T12	3319
valid_sources[0x17]	1357129	1			T1	9257		T3	2485		T12	3358
valid_sources[0x18]	1407258	1			T1	9104		T3	3945		T12	3398
valid_sources[0x19]	1364384	1			T1	9092		T2	6		T3	4144
valid_sources[0x1a]	1358424	1			T1	9249		T3	3891		T12	3313
valid_sources[0x1b]	2444711	1			T1	9009		T2	21		T3	2808
valid_sources[0x1c]	2555825	1			T1	8976		T2	46		T3	1759
valid_sources[0x1d]	1356858	1			T1	8952		T2	15		T3	4303
valid_sources[0x1e]	1363954	1			T1	9025		T2	30		T3	4506
valid_sources[0x1f]	1357350	1			T1	9142		T2	15		T3	2887
valid_sources[0x20]	1422938	1			T1	9426		T2	23		T3	3290
valid_sources[0x21]	1356471	1			T1	9508		T3	3450		T12	3304
valid_sources[0x22]	1808476	1			T1	9088		T3	3526		T12	3369
valid_sources[0x23]	2215668	1			T1	8602		T3	4001		T12	3358
valid_sources[0x24]	1569723	1			T1	8829		T2	8		T3	3399
valid_sources[0x25]	1383654	1			T1	9084		T3	4237		T12	3465
valid_sources[0x26]	2192472	1			T1	8967		T3	4195		T12	3444
valid_sources[0x27]	1345799	1			T1	9309		T3	3999		T12	3232
valid_sources[0x28]	1353059	1			T1	8951		T2	12		T3	2055
valid_sources[0x29]	1376735	1			T1	8877		T3	2508		T12	3436
valid_sources[0x2a]	1366985	1			T1	8957		T3	2488		T12	3492
valid_sources[0x2b]	3353089	1			T1	8775		T2	4		T3	2579
valid_sources[0x2c]	1354598	1			T1	8896		T3	4201		T12	3280
valid_sources[0x2d]	1514154	1			T1	9072		T3	3376		T12	3326
valid_sources[0x2e]	1702124	1			T1	8738		T2	3		T3	3147
valid_sources[0x2f]	1356582	1			T1	8972		T3	5045		T12	3350
valid_sources[0x30]	1355513	1			T1	9375		T2	17		T3	2020
valid_sources[0x31]	1365129	1			T1	8650		T3	3317		T12	3333
valid_sources[0x32]	2264446	1			T1	9195		T2	7		T3	3597
valid_sources[0x33]	1354931	1			T1	8934		T2	7		T3	3395
valid_sources[0x34]	1355589	1			T1	8866		T3	3472		T12	3351
valid_sources[0x35]	1357270	1			T1	9257		T2	24		T3	2337
valid_sources[0x36]	1360676	1			T1	9151		T2	15		T3	3565
valid_sources[0x37]	1828266	1			T1	9109		T3	3420		T12	3390
valid_sources[0x38]	4598918	1			T1	9251		T2	11		T3	3118
valid_sources[0x39]	1379345	1			T1	9279		T2	19		T3	4401
valid_sources[0x3a]	1357709	1			T1	9283		T2	3		T3	4107
valid_sources[0x3b]	1457193	1			T1	8934		T2	6		T3	3508
valid_sources[0x3c]	1431518	1			T1	9304		T2	12		T3	2684
valid_sources[0x3d]	3692630	1			T1	9107		T3	3724		T12	3461
valid_sources[0x3e]	1358042	1			T1	9205		T3	3922		T12	3483
valid_sources[0x3f]	1392981	1			T1	8896		T3	3927		T12	3359
valid_sources[0x40]	1355009	1			T1	9111		T3	3459		T12	3323
valid_sources[0x41]	3697392	1			T1	9180		T2	28		T3	3464
valid_sources[0x42]	1355924	1			T1	9061		T3	3972		T12	3398
valid_sources[0x43]	1353314	1			T1	9113		T2	49		T3	3243
valid_sources[0x44]	3501235	1			T1	9042		T2	13		T3	2630
valid_sources[0x45]	3440945	1			T1	9212		T2	11		T3	4386
valid_sources[0x46]	2251867	1			T1	8873		T2	14		T3	4661
valid_sources[0x47]	3345704	1			T1	8862		T2	14		T3	3112
valid_sources[0x48]	1368920	1			T1	9065		T3	4077		T12	3285
valid_sources[0x49]	3649561	1			T1	8748		T3	2714		T12	3319
valid_sources[0x4a]	1363861	1			T1	8822		T2	2		T3	5114
valid_sources[0x4b]	2468835	1			T1	8942		T2	33		T3	2853
valid_sources[0x4c]	2388464	1			T1	8902		T2	8		T3	3668
valid_sources[0x4d]	1356455	1			T1	8900		T2	48		T3	2222
valid_sources[0x4e]	1350352	1			T1	8813		T3	3754		T12	3287
valid_sources[0x4f]	1359363	1			T1	8945		T3	4519		T12	3338
valid_sources[0x50]	3335801	1			T1	9176		T3	3300		T12	3374
valid_sources[0x51]	1862925	1			T1	9188		T3	2667		T12	3414
valid_sources[0x52]	1369441	1			T1	9353		T2	3		T3	3497
valid_sources[0x53]	2422734	1			T1	8983		T2	8		T3	2954
valid_sources[0x54]	1355964	1			T1	9235		T2	9		T3	4566
valid_sources[0x55]	2263757	1			T1	8877		T2	7		T3	3381
valid_sources[0x56]	1358063	1			T1	8848		T3	3006		T12	3401
valid_sources[0x57]	1355168	1			T1	8938		T2	2		T3	4107
valid_sources[0x58]	2242664	1			T1	8760		T3	3646		T12	3385
valid_sources[0x59]	1362916	1			T1	9314		T3	2408		T12	3356
valid_sources[0x5a]	1359736	1			T1	9200		T3	2081		T12	3345
valid_sources[0x5b]	1349468	1			T1	9020		T2	42		T3	1962
valid_sources[0x5c]	1346956	1			T1	9207		T3	3653		T12	3316
valid_sources[0x5d]	1353513	1			T1	9250		T3	3499		T12	3340
valid_sources[0x5e]	1372121	1			T1	8854		T2	4		T3	2836
valid_sources[0x5f]	1366053	1			T1	9038		T2	38		T3	4516
valid_sources[0x60]	1354787	1			T1	8811		T3	4519		T12	3489
valid_sources[0x61]	2540501	1			T1	9113		T3	2452		T12	3357
valid_sources[0x62]	1352030	1			T1	9010		T2	6		T3	1952
valid_sources[0x63]	1360691	1			T1	8910		T2	18		T3	3922
valid_sources[0x64]	1360099	1			T1	8819		T2	1		T3	3237
valid_sources[0x65]	2018787	1			T1	8996		T3	5233		T12	3183
valid_sources[0x66]	1352205	1			T1	9197		T3	4763		T12	3390
valid_sources[0x67]	1847028	1			T1	9410		T2	1		T3	3634
valid_sources[0x68]	1348896	1			T1	8928		T2	5		T3	2485
valid_sources[0x69]	2351403	1			T1	9081		T3	4187		T12	3447
valid_sources[0x6a]	1356584	1			T1	8970		T2	23		T3	1394
valid_sources[0x6b]	1349784	1			T1	9111		T2	17		T3	2480
valid_sources[0x6c]	1363530	1			T1	9174		T3	4478		T12	3340
valid_sources[0x6d]	1358530	1			T1	8767		T3	2950		T12	3332
valid_sources[0x6e]	1348959	1			T1	9359		T3	2719		T12	3406
valid_sources[0x6f]	1478106	1			T1	9081		T3	2588		T12	3242
valid_sources[0x70]	1353733	1			T1	9144		T2	8		T3	3248
valid_sources[0x71]	1434235	1			T1	9210		T3	2956		T12	3307
valid_sources[0x72]	1390895	1			T1	9236		T3	3301		T12	3427
valid_sources[0x73]	2265786	1			T1	9365		T2	10		T3	3260
valid_sources[0x74]	1361055	1			T1	9183		T2	6		T3	5003
valid_sources[0x75]	1359662	1			T1	8668		T3	3443		T12	3369
valid_sources[0x76]	1359554	1			T1	8802		T2	9		T3	4700
valid_sources[0x77]	1411290	1			T1	8725		T3	3414		T12	3354
valid_sources[0x78]	1359133	1			T1	8835		T3	2937		T12	3287
valid_sources[0x79]	1971563	1			T1	9126		T2	36		T3	4051
valid_sources[0x7a]	1354440	1			T1	8685		T3	3654		T12	3205
valid_sources[0x7b]	1365591	1			T1	9275		T2	5		T3	2710
valid_sources[0x7c]	1361833	1			T1	8988		T3	3615		T11	2
valid_sources[0x7d]	1360427	1			T1	8832		T2	24		T3	3991
valid_sources[0x7e]	1360443	1			T1	8989		T2	31		T3	2671
valid_sources[0x7f]	1348473	1			T1	8994		T2	11		T3	1943
valid_sources[0x80]	1372947	1			T1	8804		T2	22		T3	2856

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

70774669

1

T1

335088

T2

341

T3

114232

values[0x0]

all_enables

biggest_size

60522355

1

T1

312227

T2

385

T3

113826

values[0x1]

all_enables

biggest_size

52230359

1

T1

264746

T2

377

T3

95661