Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

259393586

1

T1

140750

T2

805

T3

548253

full_word

183748634

1

T1

912061

T2

1103

T3

323719

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	443141930	1			T1	231956		T2	1908		T3	871972
auto[TlIntgErrCmd]	102	1			T121	3		T122	5		T123	4
auto[TlIntgErrData]	96	1			T121	5		T122	10		T123	6
auto[TlIntgErrBoth]	92	1			T121	2		T122	5		T172	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

227891760

1

T1

117692

T2

843

T3

437353

auto[1]

215250460

1

T1

114263

T2

1065

T3

434619

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	157061838	1			T1	841835		T2	502		T3	323121
auto[TlIntgErrNone]	partial	auto[1]	102331482	1			T1	565665		T2	303		T3	225132
auto[TlIntgErrNone]	full_word	auto[0]	70829793	1			T1	335088		T2	341		T3	114232
auto[TlIntgErrNone]	full_word	auto[1]	112918817	1			T1	576973		T2	762		T3	209487
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T121	2		T122	1		T123	1
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T121	1		T122	3		T123	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T176	1		T177	1		T178	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T122	1		T123	1		T176	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T121	4		T122	3		T123	6
auto[TlIntgErrData]	partial	auto[1]	38	1			T121	1		T122	6		T172	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T122	1		T172	1		T176	1
auto[TlIntgErrData]	full_word	auto[1]	1	1			T179	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	28	1			T122	2		T172	2		T175	3
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T121	2		T122	3		T172	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T177	1		T179	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T175	1		T173	1		T127	1