Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	817855	0	0
entropy_period_rd_A	2147483647	1524	0	0
intr_enable_rd_A	2147483647	2280	0	0
prefix_0_rd_A	2147483647	1480	0	0
prefix_10_rd_A	2147483647	1463	0	0
prefix_1_rd_A	2147483647	1510	0	0
prefix_2_rd_A	2147483647	1506	0	0
prefix_3_rd_A	2147483647	1559	0	0
prefix_4_rd_A	2147483647	1617	0	0
prefix_5_rd_A	2147483647	1566	0	0
prefix_6_rd_A	2147483647	1590	0	0
prefix_7_rd_A	2147483647	1580	0	0
prefix_8_rd_A	2147483647	1549	0	0
prefix_9_rd_A	2147483647	1543	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	817855	0	0
T44	462774	61350	0	0
T47	0	30154	0	0
T87	0	53423	0	0
T128	0	63233	0	0
T129	0	29236	0	0
T130	0	79678	0	0
T131	0	40750	0	0
T132	0	109921	0	0
T133	0	65814	0	0
T134	0	106460	0	0
T135	309319	0	0	0
T136	493451	0	0	0
T137	969485	0	0	0
T138	931858	0	0	0
T139	90237	0	0	0
T140	614263	0	0	0
T141	153635	0	0	0
T142	53860	0	0	0
T143	429240	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1524	0	0
T88	12855	43	0	0
T92	3943	10	0	0
T121	11449	29	0	0
T122	23857	57	0	0
T151	12015	20	0	0
T152	2223	2	0	0
T153	1795	5	0	0
T154	2830	10	0	0
T155	2888	15	0	0
T156	7117	16	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2280	0	0
T88	12855	46	0	0
T121	11449	18	0	0
T122	23857	102	0	0
T125	1033	26	0	0
T126	1039	11	0	0
T151	12015	44	0	0
T152	2223	5	0	0
T153	1795	10	0	0
T157	1497	7	0	0
T158	1213	2	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1480	0	0
T88	12855	17	0	0
T92	3943	8	0	0
T121	11449	11	0	0
T122	23857	29	0	0
T151	12015	18	0	0
T152	2223	1	0	0
T153	1795	1	0	0
T154	2830	6	0	0
T155	2888	7	0	0
T159	9141	10	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1463	0	0
T88	12855	25	0	0
T92	3943	12	0	0
T121	11449	24	0	0
T122	23857	41	0	0
T151	12015	87	0	0
T152	2223	4	0	0
T153	1795	7	0	0
T155	2888	6	0	0
T156	7117	17	0	0
T160	5423	25	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1510	0	0
T88	12855	34	0	0
T92	3943	15	0	0
T121	11449	20	0	0
T122	23857	42	0	0
T151	12015	28	0	0
T152	2223	6	0	0
T153	1795	3	0	0
T154	2830	2	0	0
T155	2888	9	0	0
T156	7117	19	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1506	0	0
T88	12855	17	0	0
T92	3943	8	0	0
T121	11449	20	0	0
T122	23857	28	0	0
T151	12015	40	0	0
T152	2223	2	0	0
T153	1795	4	0	0
T155	2888	12	0	0
T156	7117	7	0	0
T160	5423	13	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1559	0	0
T88	12855	30	0	0
T92	3943	3	0	0
T121	11449	19	0	0
T122	23857	16	0	0
T151	12015	46	0	0
T152	2223	4	0	0
T153	1795	4	0	0
T154	2830	6	0	0
T155	2888	6	0	0
T156	7117	14	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1617	0	0
T88	12855	35	0	0
T92	3943	9	0	0
T121	11449	28	0	0
T122	23857	47	0	0
T151	12015	54	0	0
T152	2223	7	0	0
T153	1795	2	0	0
T154	2830	6	0	0
T155	2888	3	0	0
T156	7117	15	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1566	0	0
T88	12855	22	0	0
T92	3943	3	0	0
T121	11449	29	0	0
T122	23857	62	0	0
T151	12015	56	0	0
T153	1795	6	0	0
T154	2830	9	0	0
T155	2888	5	0	0
T156	7117	14	0	0
T160	5423	16	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1590	0	0
T88	12855	32	0	0
T92	3943	5	0	0
T121	11449	9	0	0
T122	23857	60	0	0
T151	12015	42	0	0
T152	2223	1	0	0
T153	1795	2	0	0
T154	2830	7	0	0
T155	2888	12	0	0
T156	7117	13	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1580	0	0
T88	12855	49	0	0
T92	3943	3	0	0
T121	11449	14	0	0
T122	23857	32	0	0
T151	12015	66	0	0
T152	2223	5	0	0
T153	1795	3	0	0
T155	2888	4	0	0
T156	7117	7	0	0
T159	9141	3	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1549	0	0
T88	12855	30	0	0
T92	3943	6	0	0
T121	11449	14	0	0
T122	23857	34	0	0
T151	12015	11	0	0
T152	2223	3	0	0
T153	1795	1	0	0
T154	2830	6	0	0
T155	2888	7	0	0
T156	7117	22	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1543	0	0
T88	12855	35	0	0
T92	3943	5	0	0
T121	11449	27	0	0
T122	23857	33	0	0
T151	12015	17	0	0
T152	2223	9	0	0
T153	1795	4	0	0
T154	2830	9	0	0
T155	2888	13	0	0
T156	7117	16	0	0