Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

267161886

1

T1

83

T2

62

T3

406105

full_word

188475813

1

T1

1062

T2

768

T3

251633

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	455637399	1			T1	1145		T2	830		T3	657738
auto[TlIntgErrCmd]	110	1			T128	5		T129	3		T130	6
auto[TlIntgErrData]	96	1			T128	6		T129	5		T130	7
auto[TlIntgErrBoth]	94	1			T128	9		T129	2		T130	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

234132965

1

T1

73

T2

53

T3

330315

auto[1]

221504734

1

T1

1072

T2

777

T3

327423

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	161612976	1			T1	42		T2	30		T3	242219
auto[TlIntgErrNone]	partial	auto[1]	105548633	1			T1	41		T2	32		T3	163886
auto[TlIntgErrNone]	full_word	auto[0]	72519850	1			T1	31		T2	23		T3	88096
auto[TlIntgErrNone]	full_word	auto[1]	115955940	1			T1	1031		T2	745		T3	163537
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T128	1		T130	5		T179	2
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T128	3		T129	3		T130	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T128	1		T181	1		T182	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T182	1		T184	1		T185	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T128	4		T130	3		T179	6
auto[TlIntgErrData]	partial	auto[1]	43	1			T128	2		T129	5		T130	4
auto[TlIntgErrData]	full_word	auto[0]	6	1			T186	1		T187	1		T188	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T182	1		T189	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T128	4		T130	4		T179	1
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T128	5		T129	1		T130	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T179	1		T180	1		T190	2
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T129	1		T130	1		T190	1