Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
189801 |
1 |
|
|
T2 |
51 |
|
T6 |
99 |
|
T31 |
328 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
102785 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
62747 |
1 |
|
|
T2 |
50 |
|
T6 |
95 |
|
T31 |
323 |
seven_bytes |
3518 |
1 |
|
|
T6 |
1 |
|
T29 |
18 |
|
T55 |
25 |
six_bytes |
3459 |
1 |
|
|
T29 |
25 |
|
T55 |
18 |
|
T32 |
34 |
five_bytes |
3412 |
1 |
|
|
T29 |
19 |
|
T55 |
12 |
|
T32 |
28 |
four_bytes |
3462 |
1 |
|
|
T29 |
26 |
|
T55 |
23 |
|
T32 |
32 |
three_bytes |
3470 |
1 |
|
|
T29 |
12 |
|
T55 |
23 |
|
T32 |
27 |
two_bytes |
3412 |
1 |
|
|
T29 |
26 |
|
T55 |
20 |
|
T32 |
31 |
one_byte |
3536 |
1 |
|
|
T29 |
16 |
|
T55 |
19 |
|
T32 |
30 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
186307 |
1 |
|
|
T2 |
49 |
|
T6 |
93 |
|
T31 |
318 |
auto[1] |
3494 |
1 |
|
|
T2 |
2 |
|
T6 |
6 |
|
T31 |
10 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
189801 |
1 |
|
|
T2 |
51 |
|
T6 |
99 |
|
T31 |
328 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
189789 |
1 |
|
|
T2 |
51 |
|
T6 |
98 |
|
T31 |
328 |
auto[1] |
12 |
1 |
|
|
T6 |
1 |
|
T29 |
1 |
|
T166 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1155 |
1 |
|
|
T2 |
1 |
|
T6 |
3 |
|
T31 |
5 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3494 |
1 |
|
|
T2 |
2 |
|
T6 |
6 |
|
T31 |
10 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176051 |
1 |
|
|
T2 |
127 |
|
T6 |
124 |
|
T8 |
82 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
97437 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
55221 |
1 |
|
|
T2 |
123 |
|
T6 |
123 |
|
T8 |
80 |
seven_bytes |
3376 |
1 |
|
|
T29 |
30 |
|
T55 |
36 |
|
T32 |
43 |
six_bytes |
3313 |
1 |
|
|
T29 |
39 |
|
T55 |
40 |
|
T32 |
53 |
five_bytes |
3402 |
1 |
|
|
T29 |
31 |
|
T55 |
28 |
|
T32 |
49 |
four_bytes |
3422 |
1 |
|
|
T29 |
34 |
|
T55 |
29 |
|
T32 |
38 |
three_bytes |
3320 |
1 |
|
|
T29 |
36 |
|
T55 |
39 |
|
T32 |
57 |
two_bytes |
3299 |
1 |
|
|
T29 |
26 |
|
T55 |
30 |
|
T32 |
54 |
one_byte |
3261 |
1 |
|
|
T29 |
36 |
|
T55 |
36 |
|
T32 |
42 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
172831 |
1 |
|
|
T2 |
119 |
|
T6 |
122 |
|
T8 |
78 |
auto[1] |
3220 |
1 |
|
|
T2 |
8 |
|
T6 |
2 |
|
T8 |
4 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176051 |
1 |
|
|
T2 |
127 |
|
T6 |
124 |
|
T8 |
82 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176043 |
1 |
|
|
T2 |
127 |
|
T6 |
124 |
|
T8 |
82 |
auto[1] |
8 |
1 |
|
|
T167 |
1 |
|
T168 |
1 |
|
T83 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1067 |
1 |
|
|
T2 |
4 |
|
T6 |
1 |
|
T8 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3220 |
1 |
|
|
T2 |
8 |
|
T6 |
2 |
|
T8 |
4 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
342773 |
1 |
|
|
T2 |
205 |
|
T6 |
787 |
|
T8 |
53 |
auto[1] |
425 |
1 |
|
|
T21 |
94 |
|
T23 |
43 |
|
T24 |
3 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
183618 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
115656 |
1 |
|
|
T2 |
200 |
|
T6 |
210 |
|
T8 |
52 |
seven_bytes |
6250 |
1 |
|
|
T6 |
15 |
|
T29 |
24 |
|
T55 |
48 |
six_bytes |
6223 |
1 |
|
|
T6 |
15 |
|
T29 |
18 |
|
T55 |
55 |
five_bytes |
6254 |
1 |
|
|
T6 |
18 |
|
T29 |
13 |
|
T55 |
49 |
four_bytes |
6377 |
1 |
|
|
T6 |
16 |
|
T29 |
40 |
|
T55 |
46 |
three_bytes |
6306 |
1 |
|
|
T6 |
16 |
|
T29 |
29 |
|
T55 |
49 |
two_bytes |
6318 |
1 |
|
|
T6 |
19 |
|
T29 |
16 |
|
T55 |
45 |
one_byte |
6196 |
1 |
|
|
T6 |
19 |
|
T29 |
26 |
|
T55 |
49 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
336646 |
1 |
|
|
T2 |
195 |
|
T6 |
771 |
|
T8 |
51 |
auto[1] |
6552 |
1 |
|
|
T2 |
10 |
|
T6 |
16 |
|
T8 |
2 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
343198 |
1 |
|
|
T2 |
205 |
|
T6 |
787 |
|
T8 |
53 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
343176 |
1 |
|
|
T2 |
205 |
|
T6 |
787 |
|
T8 |
53 |
auto[1] |
22 |
1 |
|
|
T99 |
1 |
|
T169 |
1 |
|
T170 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2175 |
1 |
|
|
T2 |
5 |
|
T6 |
5 |
|
T8 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6552 |
1 |
|
|
T2 |
10 |
|
T6 |
16 |
|
T8 |
2 |