Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

264538231

1

T1

85590

T2

8699

T3

397942

full_word

186788619

1

T1

86963

T2

11766

T3

249419

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	451326550	1			T1	172553		T2	20465		T3	647361
auto[TlIntgErrCmd]	104	1			T114	1		T115	5		T116	7
auto[TlIntgErrData]	99	1			T114	5		T115	8		T116	6
auto[TlIntgErrBoth]	97	1			T114	4		T115	7		T116	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

232020029

1

T1

120593

T2

13430

T3

326061

auto[1]

219306821

1

T1

51960

T2

7035

T3

321300

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	160055347	1			T1	61430		T2	5594		T3	238910
auto[TlIntgErrNone]	partial	auto[1]	104482607	1			T1	24160		T2	3105		T3	159032
auto[TlIntgErrNone]	full_word	auto[0]	71964538	1			T1	59163		T2	7836		T3	87151
auto[TlIntgErrNone]	full_word	auto[1]	114824058	1			T1	27800		T2	3930		T3	162268
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T115	2		T116	3		T172	3
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T114	1		T115	2		T116	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T115	1		T177	1		T178	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T174	3		T179	1		T180	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T114	1		T115	5		T116	4
auto[TlIntgErrData]	partial	auto[1]	38	1			T114	4		T115	3		T116	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T174	1		T181	1		T176	2
auto[TlIntgErrData]	full_word	auto[1]	2	1			T176	1		T178	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T114	1		T115	5		T116	3
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T114	2		T115	2		T116	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T175	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T114	1		T116	1		T173	1