Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	799275	0	0
entropy_period_rd_A	2147483647	2307	0	0
intr_enable_rd_A	2147483647	3003	0	0
prefix_0_rd_A	2147483647	2671	0	0
prefix_10_rd_A	2147483647	2452	0	0
prefix_1_rd_A	2147483647	2536	0	0
prefix_2_rd_A	2147483647	2604	0	0
prefix_3_rd_A	2147483647	2601	0	0
prefix_4_rd_A	2147483647	2636	0	0
prefix_5_rd_A	2147483647	2581	0	0
prefix_6_rd_A	2147483647	2473	0	0
prefix_7_rd_A	2147483647	2541	0	0
prefix_8_rd_A	2147483647	2402	0	0
prefix_9_rd_A	2147483647	2472	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	799275	0	0
T4	1804	0	0	0
T5	202139	0	0	0
T6	208512	28932	0	0
T7	12463	0	0	0
T8	113168	0	0	0
T10	18394	0	0	0
T11	983	0	0	0
T12	106621	0	0	0
T40	104600	0	0	0
T42	148656	0	0	0
T55	0	38406	0	0
T76	0	64861	0	0
T121	0	46130	0	0
T122	0	28338	0	0
T123	0	24587	0	0
T124	0	74743	0	0
T125	0	16239	0	0
T126	0	39584	0	0
T127	0	197494	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2307	0	0
T32	495222	0	0	0
T35	755752	0	0	0
T55	441880	92	0	0
T58	1956	0	0	0
T88	0	17	0	0
T89	0	36	0	0
T96	0	38	0	0
T138	122997	0	0	0
T139	272410	0	0	0
T145	0	237	0	0
T146	0	3	0	0
T147	0	18	0	0
T148	0	23	0	0
T149	0	4	0	0
T150	0	5	0	0
T151	131816	0	0	0
T152	11717	0	0	0
T153	189201	0	0	0
T154	17886	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3003	0	0
T32	495222	0	0	0
T35	755752	0	0	0
T55	441880	128	0	0
T58	1956	0	0	0
T88	0	65	0	0
T89	0	62	0	0
T96	0	62	0	0
T138	122997	0	0	0
T139	272410	0	0	0
T145	0	410	0	0
T146	0	2	0	0
T147	0	19	0	0
T148	0	18	0	0
T150	0	8	0	0
T151	131816	0	0	0
T152	11717	0	0	0
T153	189201	0	0	0
T154	17886	0	0	0
T155	0	4	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2671	0	0
T32	495222	0	0	0
T35	755752	0	0	0
T55	441880	107	0	0
T58	1956	0	0	0
T88	0	18	0	0
T89	0	28	0	0
T96	0	29	0	0
T138	122997	0	0	0
T139	272410	0	0	0
T145	0	450	0	0
T147	0	20	0	0
T148	0	6	0	0
T149	0	12	0	0
T150	0	3	0	0
T151	131816	0	0	0
T152	11717	0	0	0
T153	189201	0	0	0
T154	17886	0	0	0
T155	0	2	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2452	0	0
T32	495222	0	0	0
T35	755752	0	0	0
T55	441880	115	0	0
T58	1956	0	0	0
T88	0	31	0	0
T89	0	27	0	0
T96	0	20	0	0
T138	122997	0	0	0
T139	272410	0	0	0
T145	0	456	0	0
T147	0	10	0	0
T148	0	8	0	0
T149	0	13	0	0
T150	0	10	0	0
T151	131816	0	0	0
T152	11717	0	0	0
T153	189201	0	0	0
T154	17886	0	0	0
T156	0	211	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2536	0	0
T32	495222	0	0	0
T35	755752	0	0	0
T55	441880	114	0	0
T58	1956	0	0	0
T88	0	20	0	0
T89	0	26	0	0
T96	0	29	0	0
T138	122997	0	0	0
T139	272410	0	0	0
T145	0	432	0	0
T146	0	5	0	0
T147	0	18	0	0
T148	0	12	0	0
T150	0	9	0	0
T151	131816	0	0	0
T152	11717	0	0	0
T153	189201	0	0	0
T154	17886	0	0	0
T156	0	251	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2604	0	0
T32	495222	0	0	0
T35	755752	0	0	0
T55	441880	112	0	0
T58	1956	0	0	0
T88	0	20	0	0
T89	0	25	0	0
T96	0	32	0	0
T138	122997	0	0	0
T139	272410	0	0	0
T145	0	452	0	0
T147	0	39	0	0
T148	0	3	0	0
T149	0	14	0	0
T150	0	8	0	0
T151	131816	0	0	0
T152	11717	0	0	0
T153	189201	0	0	0
T154	17886	0	0	0
T155	0	6	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2601	0	0
T32	495222	0	0	0
T35	755752	0	0	0
T55	441880	120	0	0
T58	1956	0	0	0
T88	0	18	0	0
T89	0	22	0	0
T96	0	36	0	0
T138	122997	0	0	0
T139	272410	0	0	0
T145	0	441	0	0
T146	0	2	0	0
T147	0	3	0	0
T148	0	5	0	0
T149	0	8	0	0
T150	0	5	0	0
T151	131816	0	0	0
T152	11717	0	0	0
T153	189201	0	0	0
T154	17886	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2636	0	0
T32	495222	0	0	0
T35	755752	0	0	0
T55	441880	121	0	0
T58	1956	0	0	0
T88	0	15	0	0
T89	0	31	0	0
T96	0	17	0	0
T138	122997	0	0	0
T139	272410	0	0	0
T145	0	434	0	0
T146	0	8	0	0
T147	0	8	0	0
T148	0	10	0	0
T149	0	13	0	0
T150	0	12	0	0
T151	131816	0	0	0
T152	11717	0	0	0
T153	189201	0	0	0
T154	17886	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2581	0	0
T32	495222	0	0	0
T35	755752	0	0	0
T55	441880	127	0	0
T58	1956	0	0	0
T88	0	35	0	0
T89	0	21	0	0
T96	0	19	0	0
T138	122997	0	0	0
T139	272410	0	0	0
T145	0	485	0	0
T147	0	3	0	0
T148	0	8	0	0
T150	0	12	0	0
T151	131816	0	0	0
T152	11717	0	0	0
T153	189201	0	0	0
T154	17886	0	0	0
T155	0	3	0	0
T156	0	216	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2473	0	0
T32	495222	0	0	0
T35	755752	0	0	0
T55	441880	109	0	0
T58	1956	0	0	0
T88	0	24	0	0
T89	0	16	0	0
T96	0	18	0	0
T138	122997	0	0	0
T139	272410	0	0	0
T145	0	455	0	0
T147	0	27	0	0
T148	0	8	0	0
T149	0	4	0	0
T150	0	10	0	0
T151	131816	0	0	0
T152	11717	0	0	0
T153	189201	0	0	0
T154	17886	0	0	0
T155	0	3	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2541	0	0
T32	495222	0	0	0
T35	755752	0	0	0
T55	441880	114	0	0
T58	1956	0	0	0
T88	0	23	0	0
T89	0	24	0	0
T96	0	35	0	0
T138	122997	0	0	0
T139	272410	0	0	0
T145	0	469	0	0
T146	0	7	0	0
T147	0	6	0	0
T148	0	10	0	0
T150	0	11	0	0
T151	131816	0	0	0
T152	11717	0	0	0
T153	189201	0	0	0
T154	17886	0	0	0
T156	0	238	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2402	0	0
T32	495222	0	0	0
T35	755752	0	0	0
T55	441880	93	0	0
T58	1956	0	0	0
T88	0	32	0	0
T89	0	24	0	0
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T138	122997	0	0	0
T139	272410	0	0	0
T145	0	431	0	0
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T152	11717	0	0	0
T153	189201	0	0	0
T154	17886	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2472	0	0
T32	495222	0	0	0
T35	755752	0	0	0
T55	441880	153	0	0
T58	1956	0	0	0
T88	0	43	0	0
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T138	122997	0	0	0
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T145	0	420	0	0
T147	0	23	0	0
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T152	11717	0	0	0
T153	189201	0	0	0
T154	17886	0	0	0
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T157	0	4	0	0