SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[kmac_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 321229142 | 1 | T1 | 139109 | T2 | 10545 | T3 | 1209 | ||||
auto[1] | 133978853 | 1 | T1 | 539383 | T2 | 10199 | T3 | 406 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 455207813 | 1 | T1 | 193047 | T2 | 20744 | T3 | 1615 | ||||
values[1] | 12 | 1 | T120 | 1 | T176 | 1 | T177 | 2 | ||||
values[2] | 3 | 1 | T178 | 1 | T179 | 2 | - | - | ||||
values[3] | 95 | 1 | T118 | 2 | T119 | 4 | T120 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 455207815 | 1 | T1 | 193047 | T2 | 20744 | T3 | 1615 | ||||
values[1] | 13 | 1 | T119 | 1 | T180 | 1 | T178 | 1 | ||||
values[2] | 3 | 1 | T177 | 1 | T181 | 1 | T182 | 1 | ||||
values[3] | 99 | 1 | T118 | 5 | T119 | 2 | T120 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 455207715 | 1 | T1 | 193047 | T2 | 20744 | T3 | 1615 | ||||
auto[TlIntgErrCmd] | 100 | 1 | T118 | 4 | T119 | 5 | T120 | 4 | ||||
auto[TlIntgErrData] | 98 | 1 | T118 | 5 | T119 | 3 | T120 | 3 | ||||
auto[TlIntgErrBoth] | 82 | 1 | T118 | 1 | T119 | 2 | T120 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |