Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

266454197

1

T1

112127

T2

3384

T3

559

full_word

188753798

1

T1

809199

T2

17360

T3

1056

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	455207715	1			T1	193047		T2	20744		T3	1615
auto[TlIntgErrCmd]	100	1			T118	4		T119	5		T120	4
auto[TlIntgErrData]	98	1			T118	5		T119	3		T120	3
auto[TlIntgErrBoth]	82	1			T118	1		T119	2		T120	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

234719573

1

T1

100044

T2

12265

T3

675

auto[1]

220488422

1

T1

930033

T2

8479

T3

940

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	161709154	1			T1	681060		T2	1925		T3	357
auto[TlIntgErrNone]	partial	auto[1]	104744784	1			T1	440214		T2	1459		T3	202
auto[TlIntgErrNone]	full_word	auto[0]	73010297	1			T1	319380		T2	10340		T3	318
auto[TlIntgErrNone]	full_word	auto[1]	115743480	1			T1	489819		T2	7020		T3	738
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T118	3		T119	2		T120	2
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T118	1		T119	1		T176	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T119	1		T120	1		T183	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T119	1		T120	1		T176	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T118	3		T119	1		T120	1
auto[TlIntgErrData]	partial	auto[1]	47	1			T118	2		T119	2		T120	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T184	2		T182	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1			T185	1		T186	1		T179	1
auto[TlIntgErrBoth]	partial	auto[0]	26	1			T119	1		T120	2		T176	2
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T118	1		T119	1		T120	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T187	1		T183	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T176	2		T186	1		T179	1