Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	758752	0	0
entropy_period_rd_A	2147483647	1743	0	0
intr_enable_rd_A	2147483647	2584	0	0
prefix_0_rd_A	2147483647	1979	0	0
prefix_10_rd_A	2147483647	2048	0	0
prefix_1_rd_A	2147483647	1985	0	0
prefix_2_rd_A	2147483647	2106	0	0
prefix_3_rd_A	2147483647	1860	0	0
prefix_4_rd_A	2147483647	2084	0	0
prefix_5_rd_A	2147483647	1956	0	0
prefix_6_rd_A	2147483647	1988	0	0
prefix_7_rd_A	2147483647	1816	0	0
prefix_8_rd_A	2147483647	2040	0	0
prefix_9_rd_A	2147483647	2016	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	758752	0	0
T29	34681	0	0	0
T50	132312	0	0	0
T54	0	66079	0	0
T65	125577	106442	0	0
T66	0	39865	0	0
T103	38715	0	0	0
T124	0	92358	0	0
T125	0	20258	0	0
T126	0	46195	0	0
T127	0	15883	0	0
T128	0	129148	0	0
T129	0	86141	0	0
T130	0	28138	0	0
T131	491945	0	0	0
T132	821289	0	0	0
T133	335041	0	0	0
T134	556631	0	0	0
T135	842354	0	0	0
T136	696665	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1743	0	0
T66	464245	145	0	0
T90	0	31	0	0
T97	0	60	0	0
T105	92062	0	0	0
T141	141869	0	0	0
T148	0	27	0	0
T149	0	11	0	0
T150	0	4	0	0
T151	0	17	0	0
T152	0	441	0	0
T153	0	18	0	0
T154	0	13	0	0
T155	161516	0	0	0
T156	178753	0	0	0
T157	12848	0	0	0
T158	193036	0	0	0
T159	217473	0	0	0
T160	329292	0	0	0
T161	103979	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2584	0	0
T66	464245	91	0	0
T90	0	59	0	0
T97	0	142	0	0
T105	92062	0	0	0
T121	0	9	0	0
T141	141869	0	0	0
T148	0	21	0	0
T149	0	5	0	0
T150	0	1	0	0
T151	0	12	0	0
T155	161516	0	0	0
T156	178753	0	0	0
T157	12848	0	0	0
T158	193036	0	0	0
T159	217473	0	0	0
T160	329292	0	0	0
T161	103979	0	0	0
T162	0	14	0	0
T163	0	2	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1979	0	0
T66	464245	87	0	0
T90	0	25	0	0
T97	0	60	0	0
T105	92062	0	0	0
T141	141869	0	0	0
T148	0	16	0	0
T149	0	14	0	0
T150	0	1	0	0
T152	0	388	0	0
T153	0	3	0	0
T154	0	8	0	0
T155	161516	0	0	0
T156	178753	0	0	0
T157	12848	0	0	0
T158	193036	0	0	0
T159	217473	0	0	0
T160	329292	0	0	0
T161	103979	0	0	0
T164	0	29	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2048	0	0
T66	464245	114	0	0
T88	0	5	0	0
T90	0	37	0	0
T97	0	58	0	0
T105	92062	0	0	0
T141	141869	0	0	0
T148	0	10	0	0
T149	0	26	0	0
T150	0	6	0	0
T151	0	8	0	0
T152	0	417	0	0
T153	0	13	0	0
T155	161516	0	0	0
T156	178753	0	0	0
T157	12848	0	0	0
T158	193036	0	0	0
T159	217473	0	0	0
T160	329292	0	0	0
T161	103979	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1985	0	0
T66	464245	107	0	0
T88	0	6	0	0
T90	0	16	0	0
T97	0	60	0	0
T105	92062	0	0	0
T141	141869	0	0	0
T148	0	4	0	0
T149	0	11	0	0
T150	0	3	0	0
T151	0	4	0	0
T152	0	396	0	0
T153	0	15	0	0
T155	161516	0	0	0
T156	178753	0	0	0
T157	12848	0	0	0
T158	193036	0	0	0
T159	217473	0	0	0
T160	329292	0	0	0
T161	103979	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2106	0	0
T66	464245	136	0	0
T88	0	6	0	0
T90	0	31	0	0
T97	0	38	0	0
T105	92062	0	0	0
T141	141869	0	0	0
T148	0	21	0	0
T149	0	10	0	0
T150	0	2	0	0
T152	0	447	0	0
T153	0	21	0	0
T154	0	5	0	0
T155	161516	0	0	0
T156	178753	0	0	0
T157	12848	0	0	0
T158	193036	0	0	0
T159	217473	0	0	0
T160	329292	0	0	0
T161	103979	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1860	0	0
T66	464245	109	0	0
T88	0	2	0	0
T90	0	27	0	0
T97	0	67	0	0
T105	92062	0	0	0
T141	141869	0	0	0
T148	0	7	0	0
T149	0	18	0	0
T150	0	3	0	0
T151	0	7	0	0
T152	0	445	0	0
T153	0	8	0	0
T155	161516	0	0	0
T156	178753	0	0	0
T157	12848	0	0	0
T158	193036	0	0	0
T159	217473	0	0	0
T160	329292	0	0	0
T161	103979	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2084	0	0
T66	464245	81	0	0
T88	0	7	0	0
T90	0	37	0	0
T97	0	55	0	0
T105	92062	0	0	0
T141	141869	0	0	0
T148	0	8	0	0
T149	0	31	0	0
T151	0	8	0	0
T152	0	427	0	0
T153	0	13	0	0
T154	0	11	0	0
T155	161516	0	0	0
T156	178753	0	0	0
T157	12848	0	0	0
T158	193036	0	0	0
T159	217473	0	0	0
T160	329292	0	0	0
T161	103979	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1956	0	0
T66	464245	136	0	0
T88	0	3	0	0
T90	0	32	0	0
T97	0	53	0	0
T105	92062	0	0	0
T141	141869	0	0	0
T148	0	18	0	0
T149	0	8	0	0
T150	0	9	0	0
T151	0	9	0	0
T152	0	424	0	0
T153	0	2	0	0
T155	161516	0	0	0
T156	178753	0	0	0
T157	12848	0	0	0
T158	193036	0	0	0
T159	217473	0	0	0
T160	329292	0	0	0
T161	103979	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1988	0	0
T66	464245	121	0	0
T88	0	4	0	0
T90	0	38	0	0
T97	0	62	0	0
T105	92062	0	0	0
T141	141869	0	0	0
T148	0	12	0	0
T149	0	21	0	0
T151	0	7	0	0
T152	0	408	0	0
T153	0	6	0	0
T154	0	2	0	0
T155	161516	0	0	0
T156	178753	0	0	0
T157	12848	0	0	0
T158	193036	0	0	0
T159	217473	0	0	0
T160	329292	0	0	0
T161	103979	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1816	0	0
T66	464245	80	0	0
T88	0	1	0	0
T90	0	9	0	0
T97	0	47	0	0
T105	92062	0	0	0
T141	141869	0	0	0
T148	0	10	0	0
T149	0	17	0	0
T150	0	2	0	0
T151	0	6	0	0
T152	0	400	0	0
T153	0	27	0	0
T155	161516	0	0	0
T156	178753	0	0	0
T157	12848	0	0	0
T158	193036	0	0	0
T159	217473	0	0	0
T160	329292	0	0	0
T161	103979	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2040	0	0
T66	464245	100	0	0
T88	0	1	0	0
T90	0	21	0	0
T97	0	56	0	0
T105	92062	0	0	0
T141	141869	0	0	0
T148	0	25	0	0
T149	0	22	0	0
T152	0	437	0	0
T153	0	2	0	0
T154	0	5	0	0
T155	161516	0	0	0
T156	178753	0	0	0
T157	12848	0	0	0
T158	193036	0	0	0
T159	217473	0	0	0
T160	329292	0	0	0
T161	103979	0	0	0
T164	0	22	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2016	0	0
T66	464245	72	0	0
T88	0	6	0	0
T90	0	25	0	0
T97	0	56	0	0
T105	92062	0	0	0
T141	141869	0	0	0
T148	0	10	0	0
T149	0	17	0	0
T150	0	11	0	0
T151	0	11	0	0
T152	0	484	0	0
T153	0	11	0	0
T155	161516	0	0	0
T156	178753	0	0	0
T157	12848	0	0	0
T158	193036	0	0	0
T159	217473	0	0	0
T160	329292	0	0	0
T161	103979	0	0	0