Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	261263950	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

186266564

1

T1

249735

T2

323918

T3

58467

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	231678264	1			T1	332233		T2	438149		T3	65728
values[0x0]	103677068	1			T1	156065		T2	207694		T3	16414
values[0x1]	112175182	1			T1	171415		T2	227702		T3	17529

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	203005896	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

244524618

1

T1

340393

T2

446604

T3

68042

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1996360	1			T1	2552		T2	3396		T3	363
valid_sources[0x01]	1369454	1			T1	2528		T2	3336		T3	375
valid_sources[0x02]	1337722	1			T1	2471		T2	3345		T3	325
valid_sources[0x03]	2197338	1			T1	2572		T2	3410		T3	393
valid_sources[0x04]	1722210	1			T1	2643		T2	3423		T3	372
valid_sources[0x05]	1329869	1			T1	2508		T2	3416		T3	391
valid_sources[0x06]	1338615	1			T1	2563		T2	3447		T3	377
valid_sources[0x07]	4672248	1			T1	2718		T2	3356		T3	369
valid_sources[0x08]	2192295	1			T1	2582		T2	3409		T3	378
valid_sources[0x09]	2249182	1			T1	2569		T2	3416		T3	380
valid_sources[0x0a]	1505127	1			T1	2520		T2	3317		T3	364
valid_sources[0x0b]	1334479	1			T1	2693		T2	3355		T3	382
valid_sources[0x0c]	1348916	1			T1	2669		T2	3243		T3	415
valid_sources[0x0d]	1350821	1			T1	2614		T2	3489		T3	397
valid_sources[0x0e]	1346923	1			T1	2435		T2	3427		T3	362
valid_sources[0x0f]	1371819	1			T1	2470		T2	3417		T3	398
valid_sources[0x10]	1383823	1			T1	2553		T2	3257		T3	425
valid_sources[0x11]	1334862	1			T1	2704		T2	3388		T3	359
valid_sources[0x12]	1339620	1			T1	2557		T2	3452		T3	478
valid_sources[0x13]	1348662	1			T1	2459		T2	3495		T3	341
valid_sources[0x14]	1465736	1			T1	2601		T2	3301		T3	419
valid_sources[0x15]	1633276	1			T1	2340		T2	3395		T3	439
valid_sources[0x16]	2889027	1			T1	2597		T2	3305		T3	376
valid_sources[0x17]	1541935	1			T1	2626		T2	3366		T3	404
valid_sources[0x18]	1337145	1			T1	2655		T2	3377		T3	420
valid_sources[0x19]	1352018	1			T1	2667		T2	3481		T3	417
valid_sources[0x1a]	2175759	1			T1	2474		T2	3396		T3	360
valid_sources[0x1b]	1399534	1			T1	2687		T2	3442		T3	431
valid_sources[0x1c]	1346774	1			T1	2475		T2	3413		T3	439
valid_sources[0x1d]	1502600	1			T1	2476		T2	3463		T3	369
valid_sources[0x1e]	2688302	1			T1	2770		T2	3351		T3	452
valid_sources[0x1f]	1337096	1			T1	2608		T2	3322		T3	398
valid_sources[0x20]	1336172	1			T1	2719		T2	3323		T3	420
valid_sources[0x21]	1342780	1			T1	2445		T2	3391		T3	343
valid_sources[0x22]	1346298	1			T1	2497		T2	3419		T3	434
valid_sources[0x23]	1347489	1			T1	2601		T2	3517		T3	379
valid_sources[0x24]	1350432	1			T1	2563		T2	3407		T3	369
valid_sources[0x25]	1345811	1			T1	2554		T2	3467		T3	377
valid_sources[0x26]	1338575	1			T1	2649		T2	3451		T3	388
valid_sources[0x27]	1339448	1			T1	2296		T2	3415		T3	349
valid_sources[0x28]	1342646	1			T1	2531		T2	3488		T3	399
valid_sources[0x29]	1347625	1			T1	2490		T2	3291		T3	448
valid_sources[0x2a]	2208223	1			T1	2534		T2	3492		T3	332
valid_sources[0x2b]	1587447	1			T1	2675		T2	3444		T3	373
valid_sources[0x2c]	1340891	1			T1	2606		T2	3399		T3	381
valid_sources[0x2d]	1333550	1			T1	2583		T2	3488		T3	387
valid_sources[0x2e]	1341878	1			T1	2565		T2	3353		T3	466
valid_sources[0x2f]	1341395	1			T1	2498		T2	3412		T3	376
valid_sources[0x30]	1339021	1			T1	2619		T2	3295		T3	409
valid_sources[0x31]	2453192	1			T1	2582		T2	3400		T3	325
valid_sources[0x32]	1340399	1			T1	2619		T2	3385		T3	418
valid_sources[0x33]	1347108	1			T1	2537		T2	3410		T3	335
valid_sources[0x34]	1333781	1			T1	2594		T2	3378		T3	437
valid_sources[0x35]	1427161	1			T1	2585		T2	3512		T3	442
valid_sources[0x36]	1346007	1			T1	2584		T2	3432		T3	297
valid_sources[0x37]	1341117	1			T1	2478		T2	3350		T3	394
valid_sources[0x38]	1338209	1			T1	2579		T2	3372		T3	365
valid_sources[0x39]	2323719	1			T1	2510		T2	3314		T3	362
valid_sources[0x3a]	1340943	1			T1	2686		T2	3408		T3	337
valid_sources[0x3b]	1344232	1			T1	2638		T2	3468		T3	466
valid_sources[0x3c]	2279507	1			T1	2506		T2	3369		T3	382
valid_sources[0x3d]	1353639	1			T1	2574		T2	3461		T3	348
valid_sources[0x3e]	1970652	1			T1	2623		T2	3431		T3	393
valid_sources[0x3f]	1338149	1			T1	2568		T2	3497		T3	427
valid_sources[0x40]	1803928	1			T1	2599		T2	3451		T3	395
valid_sources[0x41]	1341290	1			T1	2502		T2	3331		T3	403
valid_sources[0x42]	1338394	1			T1	2590		T2	3403		T3	402
valid_sources[0x43]	1353198	1			T1	2561		T2	3370		T3	414
valid_sources[0x44]	2116600	1			T1	2468		T2	3368		T3	358
valid_sources[0x45]	2269937	1			T1	2549		T2	3332		T3	340
valid_sources[0x46]	1425817	1			T1	2429		T2	3489		T3	437
valid_sources[0x47]	1352794	1			T1	2751		T2	3468		T3	370
valid_sources[0x48]	1344944	1			T1	2573		T2	3422		T3	411
valid_sources[0x49]	3637396	1			T1	2666		T2	3445		T3	337
valid_sources[0x4a]	1347452	1			T1	2601		T2	3437		T3	392
valid_sources[0x4b]	1790019	1			T1	2488		T2	3420		T3	370
valid_sources[0x4c]	1337915	1			T1	2611		T2	3381		T3	393
valid_sources[0x4d]	1337274	1			T1	2588		T2	3421		T3	334
valid_sources[0x4e]	1338674	1			T1	2617		T2	3390		T3	336
valid_sources[0x4f]	1513456	1			T1	2647		T2	3405		T3	465
valid_sources[0x50]	1336292	1			T1	2581		T2	3317		T3	323
valid_sources[0x51]	1335519	1			T1	2594		T2	3419		T3	357
valid_sources[0x52]	1792756	1			T1	2489		T2	3490		T3	413
valid_sources[0x53]	4796327	1			T1	2590		T2	3466		T3	385
valid_sources[0x54]	3643650	1			T1	2477		T2	3352		T3	397
valid_sources[0x55]	1344342	1			T1	2605		T2	3316		T3	387
valid_sources[0x56]	1561511	1			T1	2526		T2	3425		T3	420
valid_sources[0x57]	1411185	1			T1	2418		T2	3369		T3	409
valid_sources[0x58]	3699565	1			T1	2631		T2	3392		T3	309
valid_sources[0x59]	1334886	1			T1	2536		T2	3358		T3	387
valid_sources[0x5a]	2235777	1			T1	2541		T2	3484		T3	386
valid_sources[0x5b]	1483948	1			T1	2592		T2	3488		T3	373
valid_sources[0x5c]	1343602	1			T1	2521		T2	3456		T3	342
valid_sources[0x5d]	1340951	1			T1	2471		T2	3447		T3	344
valid_sources[0x5e]	1480425	1			T1	2607		T2	3348		T3	356
valid_sources[0x5f]	1401927	1			T1	2523		T2	3385		T3	332
valid_sources[0x60]	1362126	1			T1	2658		T2	3490		T3	441
valid_sources[0x61]	1332728	1			T1	2459		T2	3565		T3	395
valid_sources[0x62]	1783195	1			T1	2571		T2	3460		T3	394
valid_sources[0x63]	1352284	1			T1	2642		T2	3577		T3	382
valid_sources[0x64]	3321010	1			T1	2623		T2	3450		T3	371
valid_sources[0x65]	1777458	1			T1	2487		T2	3444		T3	380
valid_sources[0x66]	2005088	1			T1	2625		T2	3491		T3	372
valid_sources[0x67]	1479735	1			T1	2550		T2	3431		T3	410
valid_sources[0x68]	3446370	1			T1	2647		T2	3375		T3	376
valid_sources[0x69]	2205070	1			T1	2547		T2	3376		T3	418
valid_sources[0x6a]	1337770	1			T1	2753		T2	3433		T3	464
valid_sources[0x6b]	1342349	1			T1	2615		T2	3380		T3	402
valid_sources[0x6c]	1336135	1			T1	2585		T2	3369		T3	369
valid_sources[0x6d]	1338430	1			T1	2584		T2	3419		T3	469
valid_sources[0x6e]	1342208	1			T1	2563		T2	3300		T3	395
valid_sources[0x6f]	2161827	1			T1	2608		T2	3488		T3	420
valid_sources[0x70]	1535474	1			T1	2467		T2	3349		T3	423
valid_sources[0x71]	1453498	1			T1	2596		T2	3483		T3	445
valid_sources[0x72]	1339420	1			T1	2568		T2	3449		T3	372
valid_sources[0x73]	1345111	1			T1	2499		T2	3368		T3	404
valid_sources[0x74]	1340085	1			T1	2552		T2	3396		T3	384
valid_sources[0x75]	5667745	1			T1	2563		T2	3370		T3	338
valid_sources[0x76]	2203609	1			T1	2734		T2	3435		T3	368
valid_sources[0x77]	1336725	1			T1	2576		T2	3379		T3	391
valid_sources[0x78]	1340351	1			T1	2499		T2	3393		T3	413
valid_sources[0x79]	3961601	1			T1	2549		T2	3422		T3	396
valid_sources[0x7a]	2477917	1			T1	2647		T2	3398		T3	413
valid_sources[0x7b]	2344134	1			T1	2527		T2	3386		T3	363
valid_sources[0x7c]	1333754	1			T1	2471		T2	3405		T3	324
valid_sources[0x7d]	2051777	1			T1	2596		T2	3408		T3	439
valid_sources[0x7e]	1381180	1			T1	2524		T2	3530		T3	392
valid_sources[0x7f]	1420912	1			T1	2714		T2	3412		T3	381
valid_sources[0x80]	1338638	1			T1	2527		T2	3360		T3	379

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

72217430

1

T1

89074

T2

114188

T3

39233

values[0x0]

all_enables

biggest_size

61284406

1

T1

86936

T2

114071

T3

10186

values[0x1]

all_enables

biggest_size

52764728

1

T1

73725

T2

95659

T3

9048