Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

263985794

1

T1

409978

T2

549627

T3

41204

full_word

186436604

1

T1

249735

T2

323918

T3

58467

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	450422088	1			T1	659713		T2	873545		T3	99671
auto[TlIntgErrCmd]	103	1			T121	5		T122	9		T123	3
auto[TlIntgErrData]	103	1			T121	6		T122	7		T123	4
auto[TlIntgErrBoth]	104	1			T121	9		T122	4		T123	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

232207637

1

T1

332233

T2

438149

T3

65728

auto[1]

218214761

1

T1

327480

T2

435396

T3

33943

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	159947268	1			T1	243159		T2	323961		T3	26495
auto[TlIntgErrNone]	partial	auto[1]	104038241	1			T1	166819		T2	225666		T3	14709
auto[TlIntgErrNone]	full_word	auto[0]	72260235	1			T1	89074		T2	114188		T3	39233
auto[TlIntgErrNone]	full_word	auto[1]	114176344	1			T1	160661		T2	209730		T3	19234
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T121	1		T122	4		T123	2
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T121	4		T122	4		T123	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T178	1		T179	1		T180	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T122	1		T181	1		T179	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T121	3		T122	3		T123	2
auto[TlIntgErrData]	partial	auto[1]	54	1			T121	3		T122	4		T123	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T147	1		T178	1		T182	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T123	1		T182	1		T183	2
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T121	4		T122	2		T123	1
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T121	4		T122	2		T123	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T121	1		T175	2		T184	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T185	1		T177	1		T178	1