Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	635133	0	0
entropy_period_rd_A	2147483647	1793	0	0
intr_enable_rd_A	2147483647	2547	0	0
prefix_0_rd_A	2147483647	1814	0	0
prefix_10_rd_A	2147483647	1769	0	0
prefix_1_rd_A	2147483647	1860	0	0
prefix_2_rd_A	2147483647	1829	0	0
prefix_3_rd_A	2147483647	1900	0	0
prefix_4_rd_A	2147483647	1823	0	0
prefix_5_rd_A	2147483647	1931	0	0
prefix_6_rd_A	2147483647	1823	0	0
prefix_7_rd_A	2147483647	1856	0	0
prefix_8_rd_A	2147483647	1974	0	0
prefix_9_rd_A	2147483647	1888	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	635133	0	0
T9	351750	45614	0	0
T16	549075	0	0	0
T19	521949	0	0	0
T23	0	26692	0	0
T24	0	88896	0	0
T35	201818	0	0	0
T36	11560	0	0	0
T37	26279	0	0	0
T38	624434	0	0	0
T69	0	32722	0	0
T70	0	135996	0	0
T71	0	10115	0	0
T74	155777	0	0	0
T75	124067	0	0	0
T127	0	42998	0	0
T128	0	47972	0	0
T129	0	69789	0	0
T130	0	27531	0	0
T131	32872	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1793	0	0
T52	4028	0	0	0
T69	525741	42	0	0
T70	0	278	0	0
T71	0	50	0	0
T77	0	13	0	0
T78	0	41	0	0
T144	0	5	0	0
T145	0	36	0	0
T146	0	19	0	0
T147	0	65	0	0
T148	0	237	0	0
T149	145654	0	0	0
T150	10558	0	0	0
T151	159112	0	0	0
T152	162245	0	0	0
T153	8812	0	0	0
T154	50805	0	0	0
T155	27394	0	0	0
T156	8871	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2547	0	0
T52	4028	0	0	0
T69	525741	52	0	0
T70	0	255	0	0
T71	0	24	0	0
T77	0	39	0	0
T78	0	30	0	0
T125	0	10	0	0
T144	0	9	0	0
T149	145654	0	0	0
T150	10558	0	0	0
T151	159112	0	0	0
T152	162245	0	0	0
T153	8812	0	0	0
T154	50805	0	0	0
T155	27394	0	0	0
T156	8871	0	0	0
T157	0	15	0	0
T158	0	9	0	0
T159	0	9	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1814	0	0
T52	4028	0	0	0
T69	525741	77	0	0
T70	0	281	0	0
T71	0	27	0	0
T77	0	29	0	0
T78	0	28	0	0
T144	0	10	0	0
T145	0	30	0	0
T146	0	44	0	0
T147	0	44	0	0
T148	0	413	0	0
T149	145654	0	0	0
T150	10558	0	0	0
T151	159112	0	0	0
T152	162245	0	0	0
T153	8812	0	0	0
T154	50805	0	0	0
T155	27394	0	0	0
T156	8871	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1769	0	0
T52	4028	0	0	0
T69	525741	33	0	0
T70	0	244	0	0
T71	0	23	0	0
T77	0	18	0	0
T78	0	24	0	0
T144	0	3	0	0
T145	0	30	0	0
T146	0	14	0	0
T147	0	22	0	0
T149	145654	0	0	0
T150	10558	0	0	0
T151	159112	0	0	0
T152	162245	0	0	0
T153	8812	0	0	0
T154	50805	0	0	0
T155	27394	0	0	0
T156	8871	0	0	0
T157	0	11	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1860	0	0
T52	4028	0	0	0
T69	525741	38	0	0
T70	0	329	0	0
T71	0	38	0	0
T77	0	11	0	0
T78	0	30	0	0
T144	0	6	0	0
T145	0	25	0	0
T146	0	30	0	0
T147	0	33	0	0
T149	145654	0	0	0
T150	10558	0	0	0
T151	159112	0	0	0
T152	162245	0	0	0
T153	8812	0	0	0
T154	50805	0	0	0
T155	27394	0	0	0
T156	8871	0	0	0
T157	0	14	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1829	0	0
T52	4028	0	0	0
T69	525741	54	0	0
T70	0	247	0	0
T71	0	49	0	0
T77	0	19	0	0
T78	0	32	0	0
T144	0	6	0	0
T145	0	34	0	0
T146	0	9	0	0
T147	0	48	0	0
T149	145654	0	0	0
T150	10558	0	0	0
T151	159112	0	0	0
T152	162245	0	0	0
T153	8812	0	0	0
T154	50805	0	0	0
T155	27394	0	0	0
T156	8871	0	0	0
T157	0	8	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1900	0	0
T52	4028	0	0	0
T69	525741	66	0	0
T70	0	270	0	0
T71	0	41	0	0
T77	0	29	0	0
T78	0	29	0	0
T144	0	10	0	0
T145	0	26	0	0
T146	0	46	0	0
T147	0	48	0	0
T148	0	456	0	0
T149	145654	0	0	0
T150	10558	0	0	0
T151	159112	0	0	0
T152	162245	0	0	0
T153	8812	0	0	0
T154	50805	0	0	0
T155	27394	0	0	0
T156	8871	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1823	0	0
T52	4028	0	0	0
T69	525741	78	0	0
T70	0	279	0	0
T71	0	16	0	0
T77	0	22	0	0
T78	0	25	0	0
T144	0	5	0	0
T145	0	19	0	0
T146	0	18	0	0
T147	0	36	0	0
T149	145654	0	0	0
T150	10558	0	0	0
T151	159112	0	0	0
T152	162245	0	0	0
T153	8812	0	0	0
T154	50805	0	0	0
T155	27394	0	0	0
T156	8871	0	0	0
T157	0	13	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1931	0	0
T52	4028	0	0	0
T69	525741	39	0	0
T70	0	361	0	0
T71	0	47	0	0
T77	0	22	0	0
T78	0	20	0	0
T144	0	8	0	0
T145	0	23	0	0
T146	0	37	0	0
T147	0	57	0	0
T149	145654	0	0	0
T150	10558	0	0	0
T151	159112	0	0	0
T152	162245	0	0	0
T153	8812	0	0	0
T154	50805	0	0	0
T155	27394	0	0	0
T156	8871	0	0	0
T157	0	2	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1823	0	0
T52	4028	0	0	0
T69	525741	57	0	0
T70	0	328	0	0
T71	0	50	0	0
T77	0	24	0	0
T78	0	33	0	0
T144	0	2	0	0
T145	0	26	0	0
T146	0	22	0	0
T147	0	48	0	0
T149	145654	0	0	0
T150	10558	0	0	0
T151	159112	0	0	0
T152	162245	0	0	0
T153	8812	0	0	0
T154	50805	0	0	0
T155	27394	0	0	0
T156	8871	0	0	0
T157	0	7	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1856	0	0
T52	4028	0	0	0
T69	525741	44	0	0
T70	0	322	0	0
T71	0	48	0	0
T77	0	16	0	0
T78	0	35	0	0
T144	0	10	0	0
T145	0	20	0	0
T146	0	18	0	0
T147	0	27	0	0
T149	145654	0	0	0
T150	10558	0	0	0
T151	159112	0	0	0
T152	162245	0	0	0
T153	8812	0	0	0
T154	50805	0	0	0
T155	27394	0	0	0
T156	8871	0	0	0
T157	0	14	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1974	0	0
T52	4028	0	0	0
T69	525741	32	0	0
T70	0	283	0	0
T71	0	43	0	0
T77	0	21	0	0
T78	0	36	0	0
T144	0	3	0	0
T145	0	26	0	0
T146	0	7	0	0
T147	0	30	0	0
T149	145654	0	0	0
T150	10558	0	0	0
T151	159112	0	0	0
T152	162245	0	0	0
T153	8812	0	0	0
T154	50805	0	0	0
T155	27394	0	0	0
T156	8871	0	0	0
T157	0	4	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1888	0	0
T52	4028	0	0	0
T69	525741	46	0	0
T70	0	378	0	0
T71	0	35	0	0
T77	0	20	0	0
T78	0	36	0	0
T144	0	4	0	0
T145	0	32	0	0
T146	0	14	0	0
T147	0	19	0	0
T148	0	445	0	0
T149	145654	0	0	0
T150	10558	0	0	0
T151	159112	0	0	0
T152	162245	0	0	0
T153	8812	0	0	0
T154	50805	0	0	0
T155	27394	0	0	0
T156	8871	0	0	0