Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
180785 |
1 |
|
|
T1 |
2668 |
|
T8 |
1021 |
|
T28 |
394 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
95793 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
62388 |
1 |
|
|
T1 |
68 |
|
T8 |
315 |
|
T28 |
12 |
seven_bytes |
3317 |
1 |
|
|
T1 |
57 |
|
T8 |
20 |
|
T28 |
10 |
six_bytes |
3164 |
1 |
|
|
T1 |
64 |
|
T8 |
25 |
|
T28 |
11 |
five_bytes |
3207 |
1 |
|
|
T1 |
64 |
|
T8 |
13 |
|
T28 |
15 |
four_bytes |
3165 |
1 |
|
|
T1 |
72 |
|
T8 |
12 |
|
T28 |
15 |
three_bytes |
3349 |
1 |
|
|
T1 |
69 |
|
T8 |
24 |
|
T28 |
13 |
two_bytes |
3142 |
1 |
|
|
T1 |
87 |
|
T8 |
17 |
|
T28 |
7 |
one_byte |
3260 |
1 |
|
|
T1 |
72 |
|
T8 |
21 |
|
T28 |
13 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
177337 |
1 |
|
|
T1 |
2632 |
|
T8 |
1003 |
|
T28 |
388 |
auto[1] |
3448 |
1 |
|
|
T1 |
36 |
|
T8 |
18 |
|
T28 |
6 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
180785 |
1 |
|
|
T1 |
2668 |
|
T8 |
1021 |
|
T28 |
394 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
180775 |
1 |
|
|
T1 |
2668 |
|
T8 |
1021 |
|
T28 |
394 |
auto[1] |
10 |
1 |
|
|
T77 |
1 |
|
T10 |
1 |
|
T164 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1182 |
1 |
|
|
T1 |
9 |
|
T8 |
6 |
|
T28 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3448 |
1 |
|
|
T1 |
36 |
|
T8 |
18 |
|
T28 |
6 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176250 |
1 |
|
|
T1 |
2299 |
|
T7 |
585 |
|
T8 |
878 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
96346 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
57126 |
1 |
|
|
T1 |
58 |
|
T7 |
12 |
|
T8 |
210 |
seven_bytes |
3258 |
1 |
|
|
T1 |
48 |
|
T7 |
17 |
|
T8 |
25 |
six_bytes |
3228 |
1 |
|
|
T1 |
67 |
|
T7 |
20 |
|
T8 |
18 |
five_bytes |
3193 |
1 |
|
|
T1 |
60 |
|
T7 |
18 |
|
T8 |
22 |
four_bytes |
3330 |
1 |
|
|
T1 |
59 |
|
T7 |
14 |
|
T8 |
17 |
three_bytes |
3284 |
1 |
|
|
T1 |
74 |
|
T7 |
20 |
|
T8 |
23 |
two_bytes |
3251 |
1 |
|
|
T1 |
70 |
|
T7 |
19 |
|
T8 |
19 |
one_byte |
3234 |
1 |
|
|
T1 |
60 |
|
T7 |
22 |
|
T8 |
20 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
172906 |
1 |
|
|
T1 |
2265 |
|
T7 |
579 |
|
T8 |
864 |
auto[1] |
3344 |
1 |
|
|
T1 |
34 |
|
T7 |
6 |
|
T8 |
14 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176250 |
1 |
|
|
T1 |
2299 |
|
T7 |
585 |
|
T8 |
878 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176241 |
1 |
|
|
T1 |
2299 |
|
T7 |
585 |
|
T8 |
878 |
auto[1] |
9 |
1 |
|
|
T165 |
1 |
|
T166 |
1 |
|
T167 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1132 |
1 |
|
|
T1 |
8 |
|
T7 |
1 |
|
T8 |
5 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3344 |
1 |
|
|
T1 |
34 |
|
T7 |
6 |
|
T8 |
14 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
358386 |
1 |
|
|
T1 |
5182 |
|
T7 |
643 |
|
T8 |
1452 |
auto[1] |
564 |
1 |
|
|
T9 |
1 |
|
T10 |
76 |
|
T11 |
69 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
191083 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
122253 |
1 |
|
|
T1 |
137 |
|
T7 |
16 |
|
T8 |
595 |
seven_bytes |
6627 |
1 |
|
|
T1 |
142 |
|
T7 |
10 |
|
T8 |
27 |
six_bytes |
6463 |
1 |
|
|
T1 |
142 |
|
T7 |
22 |
|
T8 |
18 |
five_bytes |
6591 |
1 |
|
|
T1 |
139 |
|
T7 |
16 |
|
T8 |
22 |
four_bytes |
6457 |
1 |
|
|
T1 |
146 |
|
T7 |
25 |
|
T8 |
20 |
three_bytes |
6491 |
1 |
|
|
T1 |
131 |
|
T7 |
13 |
|
T8 |
22 |
two_bytes |
6568 |
1 |
|
|
T1 |
150 |
|
T7 |
12 |
|
T8 |
28 |
one_byte |
6417 |
1 |
|
|
T1 |
136 |
|
T7 |
15 |
|
T8 |
20 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
352202 |
1 |
|
|
T1 |
5122 |
|
T7 |
635 |
|
T8 |
1420 |
auto[1] |
6748 |
1 |
|
|
T1 |
60 |
|
T7 |
8 |
|
T8 |
32 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
358950 |
1 |
|
|
T1 |
5182 |
|
T7 |
643 |
|
T8 |
1452 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
358918 |
1 |
|
|
T1 |
5182 |
|
T7 |
643 |
|
T8 |
1452 |
auto[1] |
32 |
1 |
|
|
T132 |
1 |
|
T52 |
1 |
|
T77 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2300 |
1 |
|
|
T1 |
6 |
|
T7 |
2 |
|
T8 |
10 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6748 |
1 |
|
|
T1 |
60 |
|
T7 |
8 |
|
T8 |
32 |