Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

259976583

1

T1

68685

T2

625

T3

810

full_word

183849239

1

T1

75626

T2

1132

T3

1112

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	443825482	1			T1	144311		T2	1757		T3	1922
auto[TlIntgErrCmd]	126	1			T117	7		T118	4		T119	4
auto[TlIntgErrData]	105	1			T117	8		T118	8		T119	4
auto[TlIntgErrBoth]	109	1			T117	5		T118	8		T119	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

227873429

1

T1

101831

T2

719

T3

851

auto[1]

215952393

1

T1

42480

T2

1038

T3

1071

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	157144775	1			T1	49470		T2	371		T3	516
auto[TlIntgErrNone]	partial	auto[1]	102831494	1			T1	19215		T2	254		T3	294
auto[TlIntgErrNone]	full_word	auto[0]	70728493	1			T1	52361		T2	348		T3	335
auto[TlIntgErrNone]	full_word	auto[1]	113120720	1			T1	23265		T2	784		T3	777
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T117	4		T118	1		T119	2
auto[TlIntgErrCmd]	partial	auto[1]	68	1			T117	3		T118	3		T119	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T171	2		T169	2		T123	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T169	1		T173	1		-	-
auto[TlIntgErrData]	partial	auto[0]	53	1			T117	5		T118	6		T119	3
auto[TlIntgErrData]	partial	auto[1]	45	1			T117	3		T118	1		T119	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T118	1		T174	2		T170	1
auto[TlIntgErrData]	full_word	auto[1]	1	1			T175	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T117	1		T118	3		T119	1
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T117	3		T118	4		T119	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T117	1		T176	1		T169	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T118	1		T177	2		T174	1