Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	929207	0	0
entropy_period_rd_A	2147483647	1517	0	0
intr_enable_rd_A	2147483647	1820	0	0
prefix_0_rd_A	2147483647	1311	0	0
prefix_10_rd_A	2147483647	1431	0	0
prefix_1_rd_A	2147483647	1354	0	0
prefix_2_rd_A	2147483647	1444	0	0
prefix_3_rd_A	2147483647	1448	0	0
prefix_4_rd_A	2147483647	1471	0	0
prefix_5_rd_A	2147483647	1522	0	0
prefix_6_rd_A	2147483647	1435	0	0
prefix_7_rd_A	2147483647	1270	0	0
prefix_8_rd_A	2147483647	1280	0	0
prefix_9_rd_A	2147483647	1415	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	929207	0	0
T12	1302	0	0	0
T13	5063	0	0	0
T16	339141	29789	0	0
T18	144681	0	0	0
T20	508679	66904	0	0
T65	0	78321	0	0
T66	0	14169	0	0
T93	472156	0	0	0
T94	212448	0	0	0
T124	0	26182	0	0
T125	0	38989	0	0
T126	0	105259	0	0
T127	0	51587	0	0
T128	0	24591	0	0
T129	0	65445	0	0
T130	954374	0	0	0
T131	10889	0	0	0
T132	101788	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1517	0	0
T66	207214	72	0	0
T67	0	81	0	0
T82	0	39	0	0
T86	0	16	0	0
T119	0	36	0	0
T139	0	16	0	0
T140	0	52	0	0
T141	0	6	0	0
T142	0	2	0	0
T143	0	17	0	0
T144	124974	0	0	0
T145	53947	0	0	0
T146	4317	0	0	0
T147	17458	0	0	0
T148	109494	0	0	0
T149	3427	0	0	0
T150	23828	0	0	0
T151	301476	0	0	0
T152	9800	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1820	0	0
T66	207214	36	0	0
T67	0	92	0	0
T82	0	39	0	0
T119	0	52	0	0
T120	0	11	0	0
T122	0	23	0	0
T139	0	12	0	0
T140	0	69	0	0
T144	124974	0	0	0
T145	53947	0	0	0
T146	4317	0	0	0
T147	17458	0	0	0
T148	109494	0	0	0
T149	3427	0	0	0
T150	23828	0	0	0
T151	301476	0	0	0
T152	9800	0	0	0
T153	0	12	0	0
T154	0	26	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1311	0	0
T66	207214	42	0	0
T67	0	47	0	0
T82	0	26	0	0
T86	0	17	0	0
T119	0	29	0	0
T139	0	15	0	0
T140	0	45	0	0
T141	0	3	0	0
T142	0	5	0	0
T143	0	15	0	0
T144	124974	0	0	0
T145	53947	0	0	0
T146	4317	0	0	0
T147	17458	0	0	0
T148	109494	0	0	0
T149	3427	0	0	0
T150	23828	0	0	0
T151	301476	0	0	0
T152	9800	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1431	0	0
T66	207214	45	0	0
T67	0	67	0	0
T82	0	34	0	0
T86	0	12	0	0
T119	0	13	0	0
T139	0	2	0	0
T140	0	54	0	0
T141	0	1	0	0
T142	0	4	0	0
T144	124974	0	0	0
T145	53947	0	0	0
T146	4317	0	0	0
T147	17458	0	0	0
T148	109494	0	0	0
T149	3427	0	0	0
T150	23828	0	0	0
T151	301476	0	0	0
T152	9800	0	0	0
T155	0	2	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1354	0	0
T66	207214	35	0	0
T67	0	42	0	0
T82	0	18	0	0
T86	0	5	0	0
T119	0	26	0	0
T139	0	22	0	0
T140	0	53	0	0
T141	0	1	0	0
T142	0	4	0	0
T143	0	7	0	0
T144	124974	0	0	0
T145	53947	0	0	0
T146	4317	0	0	0
T147	17458	0	0	0
T148	109494	0	0	0
T149	3427	0	0	0
T150	23828	0	0	0
T151	301476	0	0	0
T152	9800	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1444	0	0
T66	207214	27	0	0
T67	0	68	0	0
T82	0	38	0	0
T86	0	14	0	0
T119	0	21	0	0
T139	0	8	0	0
T140	0	69	0	0
T141	0	1	0	0
T142	0	2	0	0
T143	0	2	0	0
T144	124974	0	0	0
T145	53947	0	0	0
T146	4317	0	0	0
T147	17458	0	0	0
T148	109494	0	0	0
T149	3427	0	0	0
T150	23828	0	0	0
T151	301476	0	0	0
T152	9800	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1448	0	0
T66	207214	56	0	0
T67	0	71	0	0
T82	0	28	0	0
T86	0	14	0	0
T119	0	34	0	0
T139	0	27	0	0
T140	0	57	0	0
T141	0	5	0	0
T142	0	2	0	0
T143	0	6	0	0
T144	124974	0	0	0
T145	53947	0	0	0
T146	4317	0	0	0
T147	17458	0	0	0
T148	109494	0	0	0
T149	3427	0	0	0
T150	23828	0	0	0
T151	301476	0	0	0
T152	9800	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1471	0	0
T66	207214	62	0	0
T67	0	63	0	0
T82	0	31	0	0
T86	0	10	0	0
T119	0	26	0	0
T139	0	38	0	0
T140	0	50	0	0
T141	0	3	0	0
T142	0	6	0	0
T144	124974	0	0	0
T145	53947	0	0	0
T146	4317	0	0	0
T147	17458	0	0	0
T148	109494	0	0	0
T149	3427	0	0	0
T150	23828	0	0	0
T151	301476	0	0	0
T152	9800	0	0	0
T156	0	2	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1522	0	0
T66	207214	63	0	0
T67	0	75	0	0
T82	0	36	0	0
T86	0	9	0	0
T119	0	23	0	0
T139	0	22	0	0
T140	0	56	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	6	0	0
T144	124974	0	0	0
T145	53947	0	0	0
T146	4317	0	0	0
T147	17458	0	0	0
T148	109494	0	0	0
T149	3427	0	0	0
T150	23828	0	0	0
T151	301476	0	0	0
T152	9800	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1435	0	0
T66	207214	62	0	0
T67	0	65	0	0
T82	0	22	0	0
T86	0	14	0	0
T119	0	30	0	0
T139	0	11	0	0
T140	0	8	0	0
T142	0	1	0	0
T143	0	3	0	0
T144	124974	0	0	0
T145	53947	0	0	0
T146	4317	0	0	0
T147	17458	0	0	0
T148	109494	0	0	0
T149	3427	0	0	0
T150	23828	0	0	0
T151	301476	0	0	0
T152	9800	0	0	0
T157	0	15	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1270	0	0
T66	207214	56	0	0
T67	0	30	0	0
T82	0	13	0	0
T86	0	13	0	0
T119	0	19	0	0
T139	0	37	0	0
T140	0	34	0	0
T142	0	4	0	0
T143	0	3	0	0
T144	124974	0	0	0
T145	53947	0	0	0
T146	4317	0	0	0
T147	17458	0	0	0
T148	109494	0	0	0
T149	3427	0	0	0
T150	23828	0	0	0
T151	301476	0	0	0
T152	9800	0	0	0
T157	0	5	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1280	0	0
T66	207214	28	0	0
T67	0	48	0	0
T82	0	16	0	0
T86	0	11	0	0
T119	0	19	0	0
T139	0	52	0	0
T140	0	49	0	0
T141	0	1	0	0
T143	0	7	0	0
T144	124974	0	0	0
T145	53947	0	0	0
T146	4317	0	0	0
T147	17458	0	0	0
T148	109494	0	0	0
T149	3427	0	0	0
T150	23828	0	0	0
T151	301476	0	0	0
T152	9800	0	0	0
T157	0	5	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1415	0	0
T66	207214	59	0	0
T67	0	85	0	0
T82	0	44	0	0
T86	0	15	0	0
T119	0	25	0	0
T139	0	8	0	0
T140	0	29	0	0
T141	0	6	0	0
T143	0	2	0	0
T144	124974	0	0	0
T145	53947	0	0	0
T146	4317	0	0	0
T147	17458	0	0	0
T148	109494	0	0	0
T149	3427	0	0	0
T150	23828	0	0	0
T151	301476	0	0	0
T152	9800	0	0	0
T157	0	9	0	0