Unified Coverage Report :: Module :: kmac_errchk

Module : kmac_errchk

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.84	94.59	94.59		86.67	93.33	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_errchk.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_errchk	93.84	94.59	94.59		86.67	93.33	100.00

---

Module Instance : tb.dut.u_errchk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.84	94.59	94.59		86.67	93.33	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.00	95.18	94.59		86.67	93.55	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : kmac_errchk

	Line No.	Total	Covered	Percent
TOTAL		74	70	94.59
ALWAYS	187	15	13	86.67
CONT_ASSIGN	236	1	1	100.00
ALWAYS	244	4	4	100.00
ALWAYS	250	4	4	100.00
ALWAYS	266	4	4	100.00
ALWAYS	278	6	6	100.00
ALWAYS	286	4	3	75.00
ALWAYS	309	6	6	100.00
ALWAYS	322	6	5	83.33
CONT_ASSIGN	376	1	1	100.00
ALWAYS	391	3	3	100.00
CONT_ASSIGN	399	1	1	100.00
ALWAYS	402	19	19	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_errchk.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_errchk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
187	1	1
188	1	1
190	1	1
193	1	1
194	1	1
			MISSING_ELSE
200	1	1
201	1	1
			MISSING_ELSE
206	1	1
207	0	1
			MISSING_ELSE
213	1	1
214	1	1
			MISSING_ELSE
219	1	1
220	0	1
			MISSING_ELSE
225	1	1
226	1	1
236	1	1
244	2	2
245	2	2
			MISSING_ELSE
250	1	1
252	1	1
254	1	1
258	1	1
			MISSING_ELSE
			MISSING_ELSE
266	1	1
268	1	1
269	1	1
270	1	1
			MISSING_ELSE
			MISSING_ELSE
278	2	2
279	2	2
280	1	1
281	1	1
			MISSING_ELSE
286	1	1
288	1	1
289	1	1
290	0	1
			MISSING_ELSE
			MISSING_ELSE
309	1	1
310	1	1
311	1	1
312	1	1
313	1	1
314	1	1
322	1	1
324	1	1
326	1	1
337	1	1
349	1	1
359	0	1
376	1	1
391	3	3
399	1	1
402	1	1
404	1	1
406	1	1
409	1	1
			MISSING_ELSE
414	1	1
415	1	1
			MISSING_ELSE
420	1	1
421	1	1
			MISSING_ELSE
426	1	1
427	1	1
428	1	1
429	1	1
			MISSING_ELSE
434	1	1
435	1	1
			MISSING_ELSE
441	1	1
453	1	1
454	1	1
			MISSING_ELSE
457	1	1
459	1	1
			MISSING_ELSE

---

Cond Coverage for Module : kmac_errchk

	Total	Covered	Percent
Conditions	74	70	94.59
Logical	74	70	94.59
Non-Logical	0	0
Event	0	0

 LINE       206
 EXPRESSION (sw_cmd_i != CmdNone)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       219
 EXPRESSION (sw_cmd_i != CmdNone)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T29,T7
1	Not Covered

 LINE       236
 EXPRESSION (err_swsequence || (err_modestrength && ((!cfg_en_unsupported_modestrength_i))) || err_entropy_ready)
             -------1------    ------------------------------2-----------------------------    --------3--------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T17,T18,T68
1	0	0	Covered	T17,T18,T68

 LINE       236
 SUB-EXPRESSION (err_modestrength && ((!cfg_en_unsupported_modestrength_i)))
                 --------1-------    -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T17,T18,T68
1	1	Covered	T17,T18,T68

 LINE       252
 EXPRESSION ((st == StIdle) && (st_d == StMsgFeed))
             -------1------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       252
 SUB-EXPRESSION (st == StIdle)
                -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       252
 SUB-EXPRESSION (st_d == StMsgFeed)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       254
 EXPRESSION 
 Number  Term
      1  (((cfg_mode_i == Sha3) && (cfg_strength_i inside {L224, L256, L384, L512})) || (((cfg_mode_i == Shake) || (cfg_mode_i == CShake)) && (cfg_strength_i inside {L128, L256}))) )

-1-	Status	Tests
0	Covered	T17,T18,T68
1	Covered	T1,T2,T3

 LINE       254
 SUB-EXPRESSION 
 Number  Term
      1  ((cfg_mode_i == Sha3) && (cfg_strength_i inside {L224, L256, L384, L512})) || 
      2  (((cfg_mode_i == Shake) || (cfg_mode_i == CShake)) && (cfg_strength_i inside {L128, L256})))

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T68
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T29,T30

 LINE       254
 SUB-EXPRESSION ((cfg_mode_i == Sha3) && (cfg_strength_i inside {L224, L256, L384, L512}))
                 ----------1---------    ------------------------2-----------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T17,T18,T68
1	1	Covered	T1,T29,T30

 LINE       254
 SUB-EXPRESSION (cfg_mode_i == Sha3)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T29,T30

 LINE       254
 SUB-EXPRESSION (((cfg_mode_i == Shake) || (cfg_mode_i == CShake)) && (cfg_strength_i inside {L128, L256}))
                 ------------------------1------------------------    ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T8,T17
1	0	Covered	T17,T18,T68
1	1	Covered	T1,T2,T3

 LINE       254
 SUB-EXPRESSION ((cfg_mode_i == Shake) || (cfg_mode_i == CShake))
                 ----------1----------    -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T29,T30
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T29,T7

 LINE       254
 SUB-EXPRESSION (cfg_mode_i == Shake)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T29,T7

 LINE       254
 SUB-EXPRESSION (cfg_mode_i == CShake)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T29,T30
1	Covered	T1,T2,T3

 LINE       268
 EXPRESSION ((st == StIdle) && (st_d == StMsgFeed) && kmac_en_i)
             -------1------    ---------2---------    ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T29,T30
1	1	1	Covered	T1,T2,T3

 LINE       268
 SUB-EXPRESSION (st == StIdle)
                -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       268
 SUB-EXPRESSION (st_d == StMsgFeed)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       269
 EXPRESSION (cfg_prefix_6B_i != kmac_pkg::EncodedStringKMAC)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T18,T68

 LINE       280
 EXPRESSION (entropy_ready_pulse_i && (st == StIdle))
             ----------1----------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       280
 SUB-EXPRESSION (st == StIdle)
                -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       288
 EXPRESSION ((st == StIdle) && (st_d == StMsgFeed) && kmac_en_i)
             -------1------    ---------2---------    ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T29,T30
1	1	1	Covered	T1,T2,T3

 LINE       288
 SUB-EXPRESSION (st == StIdle)
                -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       288
 SUB-EXPRESSION (st_d == StMsgFeed)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       399
 EXPRESSION (block_swcmd ? st : st_d)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T18,T68

 LINE       406
 EXPRESSION (((!app_active_i)) && (sw_cmd_i == CmdStart))
             --------1--------    -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       406
 SUB-EXPRESSION (sw_cmd_i == CmdStart)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (sw_cmd_i == CmdProcess)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 EXPRESSION (sw_cmd_i == CmdManualRun)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T29,T7

 LINE       428
 EXPRESSION (sw_cmd_i == CmdDone)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : kmac_errchk

Summary for FSM :: st

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	13	86.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StAbsorbed	421	Covered	T1,T2,T3
StIdle	429	Covered	T1,T2,T3
StMsgFeed	409	Covered	T1,T2,T3
StProcessing	415	Covered	T1,T2,T3
StSqueezing	427	Covered	T1,T29,T7
StTerminalError	454	Covered	T12,T13,T14

transitions	Line No.	Covered	Tests
StAbsorbed->StIdle	429	Covered	T1,T2,T3
StAbsorbed->StSqueezing	427	Covered	T1,T29,T7
StAbsorbed->StTerminalError	454	Covered	T69,T70,T71
StIdle->StMsgFeed	409	Covered	T1,T2,T3
StIdle->StTerminalError	454	Covered	T14,T22,T23
StMsgFeed->StIdle	459	Not Covered
StMsgFeed->StProcessing	415	Covered	T1,T2,T3
StMsgFeed->StTerminalError	454	Covered	T12,T13,T40
StProcessing->StAbsorbed	421	Covered	T1,T2,T3
StProcessing->StIdle	459	Covered	T16,T20,T65
StProcessing->StTerminalError	454	Covered	T41
StSqueezing->StAbsorbed	435	Covered	T1,T29,T7
StSqueezing->StIdle	459	Not Covered
StSqueezing->StTerminalError	454	Covered	T27
StTerminalError->StIdle	459	Covered	T12,T13,T14

---

Branch Coverage for Module : kmac_errchk

	Line No.	Total	Covered	Percent
Branches		60	56	93.33
TERNARY	399	2	2	100.00
CASE	190	12	10	83.33
IF	244	3	3	100.00
IF	252	3	3	100.00
IF	268	3	3	100.00
CASE	309	6	6	100.00
CASE	324	5	4	80.00
IF	391	2	2	100.00
CASE	404	13	13	100.00
IF	453	2	2	100.00
IF	457	2	2	100.00
IF	278	4	4	100.00
IF	288	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_errchk.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_errchk.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	399	(block_swcmd) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T18,T68
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	190	case (st)
-2-:	193	if ((!(sw_cmd_i inside {CmdNone, CmdStart})))
-3-:	200	if ((!(sw_cmd_i inside {CmdNone, CmdProcess})))
-4-:	206	if ((sw_cmd_i != CmdNone))
-5-:	213	if ((!(sw_cmd_i inside {CmdNone, CmdManualRun, CmdDone})))
-6-:	219	if ((sw_cmd_i != CmdNone))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
StIdle	1	-	-	-	-	Covered	T17,T18,T68
StIdle	0	-	-	-	-	Covered	T1,T2,T3
StMsgFeed	-	1	-	-	-	Covered	T17,T18,T68
StMsgFeed	-	0	-	-	-	Covered	T1,T2,T3
StProcessing	-	-	1	-	-	Not Covered
StProcessing	-	-	0	-	-	Covered	T1,T2,T3
StAbsorbed	-	-	-	1	-	Covered	T17,T18,T68
StAbsorbed	-	-	-	0	-	Covered	T1,T2,T3
StSqueezing	-	-	-	-	1	Not Covered
StSqueezing	-	-	-	-	0	Covered	T1,T29,T7
StTerminalError	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	Covered	T14,T25,T26

	LineNo.	Expression
-1-:	244	if ((!rst_ni))
-2-:	245	if ((!block_swcmd))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T17,T18,T68

	LineNo.	Expression
-1-:	252	if (((st == StIdle) && (st_d == StMsgFeed)))
-2-:	254	if ((!(((cfg_mode_i == Sha3) && (cfg_strength_i inside {L224, L256, L384, L512})) || (((cfg_mode_i == Shake) || (cfg_mode_i == CShake)) && (cfg_strength_i inside {L128, L256})))))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T17,T18,T68
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	268	if ((((st == StIdle) && (st_d == StMsgFeed)) && kmac_en_i))
-2-:	269	if ((cfg_prefix_6B_i != kmac_pkg::EncodedStringKMAC))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T17,T18,T68
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	309	case (st)

Branches:

-1-	Status	Tests
StIdle	Covered	T1,T2,T3
StMsgFeed	Covered	T1,T2,T3
StProcessing	Covered	T1,T2,T3
StAbsorbed	Covered	T1,T2,T3
StSqueezing	Covered	T1,T29,T7
default	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	324	case (1'b1)

Branches:

-1-	Status	Tests
err_swsequence	Covered	T17,T18,T68
err_modestrength	Covered	T17,T18,T68
err_prefix	Covered	T17,T18,T68
err_entropy_ready	Not Covered
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	391	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	404	case (st)
-2-:	406	if (((!app_active_i) && (sw_cmd_i == CmdStart)))
-3-:	414	if ((sw_cmd_i == CmdProcess))
-4-:	420	if (prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed_i))
-5-:	426	if ((sw_cmd_i == CmdManualRun))
-6-:	428	if ((sw_cmd_i == CmdDone))
-7-:	434	if (keccak_done_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
StIdle	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	-	-	-	-	-	Covered	T1,T2,T3
StMsgFeed	-	1	-	-	-	-	Covered	T1,T2,T3
StMsgFeed	-	0	-	-	-	-	Covered	T1,T2,T3
StProcessing	-	-	1	-	-	-	Covered	T1,T2,T3
StProcessing	-	-	0	-	-	-	Covered	T1,T2,T3
StAbsorbed	-	-	-	1	-	-	Covered	T1,T29,T7
StAbsorbed	-	-	-	0	1	-	Covered	T1,T2,T3
StAbsorbed	-	-	-	0	0	-	Covered	T1,T2,T3
StSqueezing	-	-	-	-	-	1	Covered	T1,T29,T7
StSqueezing	-	-	-	-	-	0	Covered	T1,T29,T7
StTerminalError	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	Covered	T14,T25,T26

	LineNo.	Expression
-1-:	453	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	457	if (((st_d != StTerminalError) && prim_mubi_pkg::mubi4_test_true_strict(clear_after_error_i)))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	278	if ((!rst_ni))
-2-:	279	if (err_processed_i)
-3-:	280	if ((entropy_ready_pulse_i && (st == StIdle)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T36,T4,T5
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	288	if ((((st == StIdle) && (st_d == StMsgFeed)) && kmac_en_i))
-2-:	289	if ((!cfg_entropy_ready))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

---

Assert Coverage for Module : kmac_errchk

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ExpectedModeStrengthBits_A	1029	1029	0	0
ExpectedStSwCmdBits_A	1029	1029	0	0
StKnown_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

ExpectedModeStrengthBits_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1029	1029	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

ExpectedStSwCmdBits_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1029	1029	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

StKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	888285	888206	0	0
T2	24523	24461	0	0
T3	12406	12308	0	0
T7	194164	194065	0	0
T8	298580	298501	0	0
T29	222341	222257	0	0
T30	495056	495046	0	0
T31	785359	785294	0	0
T32	1638	1551	0	0
T33	10890	10817	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	888285	888206	0	0
T2	24523	24461	0	0
T3	12406	12308	0	0
T7	194164	194065	0	0
T8	298580	298501	0	0
T29	222341	222257	0	0
T30	495056	495046	0	0
T31	785359	785294	0	0
T32	1638	1551	0	0
T33	10890	10817	0	0