Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

263780403

1

T1

620

T2

26330

T3

2640

full_word

185232077

1

T1

770

T2

39431

T3

4038

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	449012200	1			T1	1390		T2	65761		T3	6678
auto[TlIntgErrCmd]	92	1			T138	5		T139	6		T140	7
auto[TlIntgErrData]	102	1			T138	9		T139	2		T140	7
auto[TlIntgErrBoth]	86	1			T138	6		T139	2		T140	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

231341924

1

T1

891

T2

43581

T3

4670

auto[1]

217670556

1

T1

499

T2

22180

T3

2008

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	160029401	1			T1	355		T2	17098		T3	1701
auto[TlIntgErrNone]	partial	auto[1]	103750739	1			T1	265		T2	9232		T3	939
auto[TlIntgErrNone]	full_word	auto[0]	71312387	1			T1	536		T2	26483		T3	2969
auto[TlIntgErrNone]	full_word	auto[1]	113919673	1			T1	234		T2	12948		T3	1069
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T138	4		T139	3		T140	5
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T138	1		T139	2		T140	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T190	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T139	1		T140	1		T192	1
auto[TlIntgErrData]	partial	auto[0]	49	1			T138	6		T139	1		T140	2
auto[TlIntgErrData]	partial	auto[1]	47	1			T138	3		T140	4		T166	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T139	1		T140	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T193	1		T194	1		T191	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T138	2		T139	2		T140	4
auto[TlIntgErrBoth]	partial	auto[1]	41	1			T138	2		T140	2		T166	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T138	2		T194	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T195	1		T196	1		T197	1