Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	880413	0	0
entropy_period_rd_A	2147483647	2484	0	0
intr_enable_rd_A	2147483647	3034	0	0
prefix_0_rd_A	2147483647	2317	0	0
prefix_10_rd_A	2147483647	2262	0	0
prefix_1_rd_A	2147483647	2320	0	0
prefix_2_rd_A	2147483647	2242	0	0
prefix_3_rd_A	2147483647	2348	0	0
prefix_4_rd_A	2147483647	2162	0	0
prefix_5_rd_A	2147483647	2387	0	0
prefix_6_rd_A	2147483647	2337	0	0
prefix_7_rd_A	2147483647	2348	0	0
prefix_8_rd_A	2147483647	2403	0	0
prefix_9_rd_A	2147483647	2418	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	880413	0	0
T5	86986	0	0	0
T13	3048	0	0	0
T16	570080	84975	0	0
T17	0	15951	0	0
T26	0	48527	0	0
T54	0	184042	0	0
T55	0	45870	0	0
T144	0	22632	0	0
T145	0	42746	0	0
T146	0	48942	0	0
T147	0	25701	0	0
T148	0	89466	0	0
T149	24166	0	0	0
T150	206345	0	0	0
T151	200640	0	0	0
T152	8278	0	0	0
T153	25212	0	0	0
T154	230400	0	0	0
T155	201522	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2484	0	0
T55	527652	114	0	0
T74	183700	0	0	0
T87	1852	0	0	0
T91	0	59	0	0
T92	0	99	0	0
T96	0	16	0	0
T128	104805	0	0	0
T143	0	6	0	0
T162	259286	0	0	0
T163	0	2	0	0
T164	0	215	0	0
T165	0	5	0	0
T166	0	109	0	0
T167	0	119	0	0
T168	289380	0	0	0
T169	618907	0	0	0
T170	17393	0	0	0
T171	165316	0	0	0
T172	516898	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3034	0	0
T55	527652	93	0	0
T74	183700	0	0	0
T87	1852	0	0	0
T91	0	32	0	0
T92	0	98	0	0
T95	0	3	0	0
T96	0	13	0	0
T128	104805	0	0	0
T143	0	8	0	0
T162	259286	0	0	0
T163	0	5	0	0
T168	289380	0	0	0
T169	618907	0	0	0
T170	17393	0	0	0
T171	165316	0	0	0
T172	516898	0	0	0
T173	0	13	0	0
T174	0	14	0	0
T175	0	11	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2317	0	0
T55	527652	130	0	0
T74	183700	0	0	0
T87	1852	0	0	0
T91	0	29	0	0
T92	0	79	0	0
T95	0	3	0	0
T96	0	6	0	0
T101	0	4	0	0
T128	104805	0	0	0
T143	0	3	0	0
T162	259286	0	0	0
T163	0	13	0	0
T164	0	245	0	0
T165	0	8	0	0
T168	289380	0	0	0
T169	618907	0	0	0
T170	17393	0	0	0
T171	165316	0	0	0
T172	516898	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2262	0	0
T55	527652	73	0	0
T74	183700	0	0	0
T87	1852	0	0	0
T91	0	34	0	0
T92	0	62	0	0
T95	0	15	0	0
T96	0	12	0	0
T128	104805	0	0	0
T143	0	3	0	0
T162	259286	0	0	0
T163	0	10	0	0
T164	0	199	0	0
T165	0	2	0	0
T166	0	43	0	0
T168	289380	0	0	0
T169	618907	0	0	0
T170	17393	0	0	0
T171	165316	0	0	0
T172	516898	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2320	0	0
T55	527652	98	0	0
T74	183700	0	0	0
T87	1852	0	0	0
T91	0	44	0	0
T92	0	73	0	0
T96	0	13	0	0
T128	104805	0	0	0
T143	0	7	0	0
T162	259286	0	0	0
T163	0	2	0	0
T164	0	274	0	0
T165	0	2	0	0
T166	0	43	0	0
T167	0	97	0	0
T168	289380	0	0	0
T169	618907	0	0	0
T170	17393	0	0	0
T171	165316	0	0	0
T172	516898	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2242	0	0
T55	527652	113	0	0
T74	183700	0	0	0
T87	1852	0	0	0
T91	0	48	0	0
T92	0	83	0	0
T95	0	12	0	0
T96	0	25	0	0
T101	0	7	0	0
T128	104805	0	0	0
T143	0	2	0	0
T162	259286	0	0	0
T163	0	9	0	0
T164	0	210	0	0
T166	0	37	0	0
T168	289380	0	0	0
T169	618907	0	0	0
T170	17393	0	0	0
T171	165316	0	0	0
T172	516898	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2348	0	0
T55	527652	113	0	0
T74	183700	0	0	0
T87	1852	0	0	0
T91	0	45	0	0
T92	0	132	0	0
T95	0	5	0	0
T96	0	8	0	0
T128	104805	0	0	0
T143	0	7	0	0
T162	259286	0	0	0
T164	0	207	0	0
T165	0	1	0	0
T166	0	35	0	0
T167	0	58	0	0
T168	289380	0	0	0
T169	618907	0	0	0
T170	17393	0	0	0
T171	165316	0	0	0
T172	516898	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2162	0	0
T55	527652	82	0	0
T74	183700	0	0	0
T87	1852	0	0	0
T91	0	44	0	0
T92	0	77	0	0
T95	0	9	0	0
T96	0	25	0	0
T101	0	2	0	0
T128	104805	0	0	0
T143	0	13	0	0
T162	259286	0	0	0
T163	0	3	0	0
T164	0	219	0	0
T165	0	4	0	0
T168	289380	0	0	0
T169	618907	0	0	0
T170	17393	0	0	0
T171	165316	0	0	0
T172	516898	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2387	0	0
T55	527652	146	0	0
T74	183700	0	0	0
T87	1852	0	0	0
T91	0	37	0	0
T92	0	116	0	0
T96	0	21	0	0
T101	0	9	0	0
T128	104805	0	0	0
T143	0	12	0	0
T162	259286	0	0	0
T164	0	196	0	0
T165	0	3	0	0
T166	0	39	0	0
T167	0	91	0	0
T168	289380	0	0	0
T169	618907	0	0	0
T170	17393	0	0	0
T171	165316	0	0	0
T172	516898	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2337	0	0
T55	527652	115	0	0
T74	183700	0	0	0
T87	1852	0	0	0
T91	0	40	0	0
T92	0	100	0	0
T96	0	23	0	0
T128	104805	0	0	0
T143	0	4	0	0
T162	259286	0	0	0
T164	0	222	0	0
T165	0	10	0	0
T166	0	36	0	0
T167	0	97	0	0
T168	289380	0	0	0
T169	618907	0	0	0
T170	17393	0	0	0
T171	165316	0	0	0
T172	516898	0	0	0
T176	0	229	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2348	0	0
T55	527652	116	0	0
T74	183700	0	0	0
T87	1852	0	0	0
T91	0	49	0	0
T92	0	72	0	0
T95	0	11	0	0
T96	0	15	0	0
T128	104805	0	0	0
T143	0	5	0	0
T162	259286	0	0	0
T163	0	1	0	0
T164	0	272	0	0
T166	0	44	0	0
T167	0	59	0	0
T168	289380	0	0	0
T169	618907	0	0	0
T170	17393	0	0	0
T171	165316	0	0	0
T172	516898	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2403	0	0
T55	527652	123	0	0
T74	183700	0	0	0
T87	1852	0	0	0
T91	0	44	0	0
T92	0	100	0	0
T96	0	13	0	0
T128	104805	0	0	0
T143	0	9	0	0
T162	259286	0	0	0
T164	0	232	0	0
T165	0	8	0	0
T166	0	44	0	0
T167	0	87	0	0
T168	289380	0	0	0
T169	618907	0	0	0
T170	17393	0	0	0
T171	165316	0	0	0
T172	516898	0	0	0
T176	0	236	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2418	0	0
T55	527652	160	0	0
T74	183700	0	0	0
T87	1852	0	0	0
T91	0	40	0	0
T92	0	90	0	0
T95	0	5	0	0
T96	0	37	0	0
T101	0	4	0	0
T128	104805	0	0	0
T143	0	2	0	0
T162	259286	0	0	0
T164	0	245	0	0
T166	0	36	0	0
T167	0	76	0	0
T168	289380	0	0	0
T169	618907	0	0	0
T170	17393	0	0	0
T171	165316	0	0	0
T172	516898	0	0	0