Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176876 |
1 |
|
|
T2 |
990 |
|
T6 |
77 |
|
T7 |
89 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
94907 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
59251 |
1 |
|
|
T2 |
26 |
|
T6 |
76 |
|
T7 |
87 |
seven_bytes |
3321 |
1 |
|
|
T2 |
21 |
|
T18 |
17 |
|
T17 |
21 |
six_bytes |
3375 |
1 |
|
|
T2 |
22 |
|
T18 |
19 |
|
T17 |
36 |
five_bytes |
3269 |
1 |
|
|
T2 |
33 |
|
T18 |
18 |
|
T17 |
21 |
four_bytes |
3184 |
1 |
|
|
T2 |
27 |
|
T18 |
22 |
|
T17 |
35 |
three_bytes |
3078 |
1 |
|
|
T2 |
23 |
|
T18 |
12 |
|
T17 |
15 |
two_bytes |
3280 |
1 |
|
|
T2 |
33 |
|
T18 |
20 |
|
T17 |
37 |
one_byte |
3211 |
1 |
|
|
T2 |
31 |
|
T18 |
19 |
|
T17 |
34 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
173598 |
1 |
|
|
T2 |
980 |
|
T6 |
75 |
|
T7 |
85 |
auto[1] |
3278 |
1 |
|
|
T2 |
10 |
|
T6 |
2 |
|
T7 |
4 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176876 |
1 |
|
|
T2 |
990 |
|
T6 |
77 |
|
T7 |
89 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176865 |
1 |
|
|
T2 |
990 |
|
T6 |
77 |
|
T7 |
89 |
auto[1] |
11 |
1 |
|
|
T174 |
1 |
|
T175 |
1 |
|
T176 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1116 |
1 |
|
|
T2 |
2 |
|
T6 |
1 |
|
T7 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3278 |
1 |
|
|
T2 |
10 |
|
T6 |
2 |
|
T7 |
4 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
168184 |
1 |
|
|
T2 |
1484 |
|
T6 |
14 |
|
T7 |
129 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
90284 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
56140 |
1 |
|
|
T2 |
266 |
|
T6 |
13 |
|
T7 |
127 |
seven_bytes |
3118 |
1 |
|
|
T2 |
34 |
|
T18 |
23 |
|
T17 |
42 |
six_bytes |
3166 |
1 |
|
|
T2 |
45 |
|
T18 |
17 |
|
T17 |
36 |
five_bytes |
3148 |
1 |
|
|
T2 |
42 |
|
T18 |
14 |
|
T17 |
35 |
four_bytes |
3152 |
1 |
|
|
T2 |
43 |
|
T18 |
28 |
|
T17 |
43 |
three_bytes |
3190 |
1 |
|
|
T2 |
32 |
|
T18 |
21 |
|
T17 |
35 |
two_bytes |
2923 |
1 |
|
|
T2 |
24 |
|
T18 |
23 |
|
T17 |
38 |
one_byte |
3063 |
1 |
|
|
T2 |
27 |
|
T18 |
22 |
|
T17 |
33 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
165050 |
1 |
|
|
T2 |
1464 |
|
T6 |
12 |
|
T7 |
125 |
auto[1] |
3134 |
1 |
|
|
T2 |
20 |
|
T6 |
2 |
|
T7 |
4 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
168184 |
1 |
|
|
T2 |
1484 |
|
T6 |
14 |
|
T7 |
129 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
168180 |
1 |
|
|
T2 |
1484 |
|
T6 |
14 |
|
T7 |
129 |
auto[1] |
4 |
1 |
|
|
T177 |
1 |
|
T178 |
1 |
|
T176 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1070 |
1 |
|
|
T2 |
6 |
|
T6 |
1 |
|
T7 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3134 |
1 |
|
|
T2 |
20 |
|
T6 |
2 |
|
T7 |
4 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
336501 |
1 |
|
|
T2 |
2248 |
|
T6 |
149 |
|
T7 |
177 |
auto[1] |
395 |
1 |
|
|
T8 |
30 |
|
T9 |
1 |
|
T10 |
74 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
181488 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
112167 |
1 |
|
|
T2 |
417 |
|
T6 |
146 |
|
T7 |
174 |
seven_bytes |
6199 |
1 |
|
|
T2 |
56 |
|
T18 |
60 |
|
T17 |
96 |
six_bytes |
6127 |
1 |
|
|
T2 |
45 |
|
T18 |
40 |
|
T17 |
95 |
five_bytes |
6195 |
1 |
|
|
T2 |
47 |
|
T18 |
54 |
|
T17 |
85 |
four_bytes |
6212 |
1 |
|
|
T2 |
59 |
|
T18 |
48 |
|
T17 |
104 |
three_bytes |
6190 |
1 |
|
|
T2 |
53 |
|
T18 |
43 |
|
T17 |
99 |
two_bytes |
6179 |
1 |
|
|
T2 |
38 |
|
T18 |
43 |
|
T17 |
87 |
one_byte |
6139 |
1 |
|
|
T2 |
48 |
|
T18 |
40 |
|
T17 |
81 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
330573 |
1 |
|
|
T2 |
2214 |
|
T6 |
143 |
|
T7 |
171 |
auto[1] |
6323 |
1 |
|
|
T2 |
34 |
|
T6 |
6 |
|
T7 |
6 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
336896 |
1 |
|
|
T2 |
2248 |
|
T6 |
149 |
|
T7 |
177 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
336883 |
1 |
|
|
T2 |
2248 |
|
T6 |
149 |
|
T7 |
177 |
auto[1] |
13 |
1 |
|
|
T90 |
1 |
|
T179 |
1 |
|
T127 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2134 |
1 |
|
|
T2 |
9 |
|
T6 |
3 |
|
T7 |
3 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6323 |
1 |
|
|
T2 |
34 |
|
T6 |
6 |
|
T7 |
6 |