Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	262003312	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

187660276

1

T1

341241

T2

310208

T3

57

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	232965130	1			T1	128048		T2	317204		T3	21
values[0x0]	104081260	1			T1	138450		T2	148568		T3	37
values[0x1]	112617198	1			T1	139030		T2	158149		T3	22

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	203532160	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

246131428

1

T1

358256

T2

380806

T3

63

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2110248	1			T1	1618		T2	2488		T4	1
valid_sources[0x01]	1341618	1			T1	1574		T2	2366		T30	7844
valid_sources[0x02]	1425001	1			T1	1600		T2	2495		T30	7862
valid_sources[0x03]	2900985	1			T1	1616		T2	2248		T30	7988
valid_sources[0x04]	2305476	1			T1	1589		T2	2381		T30	7782
valid_sources[0x05]	1366500	1			T1	1588		T2	2775		T30	7610
valid_sources[0x06]	1450589	1			T1	1498		T2	2363		T30	7767
valid_sources[0x07]	1415698	1			T1	1618		T2	2936		T4	3
valid_sources[0x08]	1325657	1			T1	1624		T2	3022		T4	5
valid_sources[0x09]	1575147	1			T1	1548		T2	2039		T30	7736
valid_sources[0x0a]	1773828	1			T1	1531		T2	2423		T30	7662
valid_sources[0x0b]	1974376	1			T1	1685		T2	1686		T30	7954
valid_sources[0x0c]	4098586	1			T1	1548		T2	2624		T4	5
valid_sources[0x0d]	1301356	1			T1	1553		T2	2152		T4	1
valid_sources[0x0e]	1306246	1			T1	1582		T2	2653		T30	7721
valid_sources[0x0f]	1312146	1			T1	1606		T2	2400		T30	7980
valid_sources[0x10]	1586830	1			T1	1613		T2	2354		T30	7863
valid_sources[0x11]	1307915	1			T1	1619		T2	2405		T30	7854
valid_sources[0x12]	1308526	1			T1	1531		T2	2455		T30	7822
valid_sources[0x13]	2255512	1			T1	1648		T2	2351		T30	8013
valid_sources[0x14]	3888971	1			T1	1640		T2	2519		T30	7698
valid_sources[0x15]	1731996	1			T1	1568		T2	2407		T30	7973
valid_sources[0x16]	1381545	1			T1	1521		T2	2210		T30	7747
valid_sources[0x17]	1378394	1			T1	1658		T2	2047		T30	7762
valid_sources[0x18]	1307393	1			T1	1622		T2	2428		T4	3
valid_sources[0x19]	1310707	1			T1	1577		T2	2646		T30	7731
valid_sources[0x1a]	1414137	1			T1	1669		T2	2817		T30	7746
valid_sources[0x1b]	1401758	1			T1	1516		T2	2214		T30	7874
valid_sources[0x1c]	1821043	1			T1	1642		T2	2344		T30	7601
valid_sources[0x1d]	1300502	1			T1	1604		T2	2484		T4	1
valid_sources[0x1e]	1310825	1			T1	1625		T2	2187		T30	7873
valid_sources[0x1f]	1767417	1			T1	1614		T2	2153		T30	7757
valid_sources[0x20]	1768836	1			T1	1579		T2	2315		T30	7965
valid_sources[0x21]	3255434	1			T1	1500		T2	2202		T30	8072
valid_sources[0x22]	1306885	1			T1	1570		T2	2356		T30	7844
valid_sources[0x23]	1302725	1			T1	1582		T2	2182		T30	7810
valid_sources[0x24]	1960450	1			T1	1574		T2	2875		T30	7723
valid_sources[0x25]	1305627	1			T1	1475		T2	2341		T30	7894
valid_sources[0x26]	1315028	1			T1	1592		T2	3023		T30	7951
valid_sources[0x27]	1312175	1			T1	1550		T2	2882		T30	7739
valid_sources[0x28]	2479246	1			T1	1574		T2	2083		T30	8023
valid_sources[0x29]	3528839	1			T1	1605		T2	2055		T30	7838
valid_sources[0x2a]	1306296	1			T1	1628		T2	2401		T30	7944
valid_sources[0x2b]	2142814	1			T1	1590		T2	2241		T4	1
valid_sources[0x2c]	1310636	1			T1	1601		T2	2561		T30	7875
valid_sources[0x2d]	1408297	1			T1	1638		T2	2604		T30	7730
valid_sources[0x2e]	1309972	1			T1	1662		T2	2331		T30	7919
valid_sources[0x2f]	1307055	1			T1	1564		T2	2550		T4	1
valid_sources[0x30]	1309255	1			T1	1563		T2	2794		T30	8127
valid_sources[0x31]	1309774	1			T1	1528		T2	3018		T30	7991
valid_sources[0x32]	1304917	1			T1	1656		T2	2487		T30	7652
valid_sources[0x33]	1303634	1			T1	1592		T2	2410		T30	7750
valid_sources[0x34]	1297254	1			T1	1539		T2	2677		T30	7862
valid_sources[0x35]	1339266	1			T1	1612		T2	2450		T30	7960
valid_sources[0x36]	1385555	1			T1	1568		T2	2188		T30	7799
valid_sources[0x37]	1299201	1			T1	1691		T2	2580		T30	7856
valid_sources[0x38]	1310857	1			T1	1612		T2	2482		T30	7813
valid_sources[0x39]	3261959	1			T1	1574		T2	2456		T30	7839
valid_sources[0x3a]	1314153	1			T1	1557		T2	2926		T4	3
valid_sources[0x3b]	1714304	1			T1	1623		T2	2915		T30	7996
valid_sources[0x3c]	1313569	1			T1	1596		T2	2380		T30	7952
valid_sources[0x3d]	1315965	1			T1	1567		T2	2215		T30	7905
valid_sources[0x3e]	2137485	1			T1	1582		T2	3240		T30	8013
valid_sources[0x3f]	2874203	1			T1	1646		T2	2331		T30	7843
valid_sources[0x40]	1979640	1			T1	1576		T2	2304		T30	7930
valid_sources[0x41]	1310914	1			T1	1542		T2	2938		T30	7968
valid_sources[0x42]	1318890	1			T1	1658		T2	1988		T4	4
valid_sources[0x43]	1309225	1			T1	1578		T2	2756		T4	1
valid_sources[0x44]	1307323	1			T1	1518		T2	2409		T30	8031
valid_sources[0x45]	1982316	1			T1	1560		T2	2130		T30	7897
valid_sources[0x46]	1364964	1			T1	1637		T2	2241		T30	8000
valid_sources[0x47]	6021320	1			T1	1513		T2	2011		T4	2
valid_sources[0x48]	1469018	1			T1	1519		T2	2148		T4	5
valid_sources[0x49]	1306574	1			T1	1545		T2	2540		T30	8058
valid_sources[0x4a]	1304091	1			T1	1603		T2	2477		T30	8025
valid_sources[0x4b]	3349066	1			T1	1593		T2	2659		T4	1
valid_sources[0x4c]	1313306	1			T1	1604		T2	2425		T4	1
valid_sources[0x4d]	1397381	1			T1	1589		T2	2089		T30	7910
valid_sources[0x4e]	2177642	1			T1	1571		T2	2634		T30	7705
valid_sources[0x4f]	1303599	1			T1	1665		T2	2494		T4	2
valid_sources[0x50]	1312002	1			T1	1591		T2	2625		T30	7772
valid_sources[0x51]	1312224	1			T1	1485		T2	2886		T30	7817
valid_sources[0x52]	1311658	1			T1	1705		T2	2001		T30	8068
valid_sources[0x53]	1314637	1			T1	1672		T2	2690		T4	2
valid_sources[0x54]	1307391	1			T1	1693		T2	2778		T4	2
valid_sources[0x55]	2192774	1			T1	1632		T2	2620		T30	7831
valid_sources[0x56]	1311962	1			T1	1705		T2	2478		T30	7725
valid_sources[0x57]	1341934	1			T1	1738		T2	2237		T30	7915
valid_sources[0x58]	1305884	1			T1	1637		T2	2783		T30	7897
valid_sources[0x59]	1310252	1			T1	1600		T2	2316		T4	3
valid_sources[0x5a]	2123354	1			T1	1625		T2	2335		T30	7994
valid_sources[0x5b]	1314177	1			T1	1593		T2	2289		T4	1
valid_sources[0x5c]	1362407	1			T1	1443		T2	2006		T30	7755
valid_sources[0x5d]	1310357	1			T1	1589		T2	2442		T30	7796
valid_sources[0x5e]	1810329	1			T1	1633		T2	2176		T4	3
valid_sources[0x5f]	1311886	1			T1	1582		T2	2227		T30	7630
valid_sources[0x60]	1306301	1			T1	1572		T2	2090		T4	2
valid_sources[0x61]	1309736	1			T1	1585		T2	1996		T30	7922
valid_sources[0x62]	1914716	1			T1	1627		T2	2031		T30	7834
valid_sources[0x63]	1326700	1			T1	1679		T2	2781		T4	1
valid_sources[0x64]	1314804	1			T1	1542		T2	2574		T4	1
valid_sources[0x65]	1315850	1			T1	1543		T2	2499		T4	11
valid_sources[0x66]	1301562	1			T1	1556		T2	2532		T30	7798
valid_sources[0x67]	2115290	1			T1	1558		T2	2483		T30	7781
valid_sources[0x68]	1311013	1			T1	1569		T2	2804		T30	7857
valid_sources[0x69]	1314093	1			T1	1675		T2	2607		T4	3
valid_sources[0x6a]	1315680	1			T1	1597		T2	2166		T30	7763
valid_sources[0x6b]	1308346	1			T1	1522		T2	2064		T30	7872
valid_sources[0x6c]	1308327	1			T1	1555		T2	2313		T30	8013
valid_sources[0x6d]	1307960	1			T1	1654		T2	3340		T4	2
valid_sources[0x6e]	1310967	1			T1	1658		T2	2617		T30	7876
valid_sources[0x6f]	1302681	1			T1	1547		T2	2492		T30	7951
valid_sources[0x70]	1478852	1			T1	1563		T2	2374		T30	7935
valid_sources[0x71]	1309899	1			T1	1627		T2	2128		T30	8021
valid_sources[0x72]	1315646	1			T1	1623		T2	2446		T4	4
valid_sources[0x73]	2207051	1			T1	1539		T2	2327		T30	8023
valid_sources[0x74]	1309548	1			T1	1566		T2	2558		T4	10
valid_sources[0x75]	1310955	1			T1	1603		T2	2686		T30	7817
valid_sources[0x76]	1328937	1			T1	1570		T2	2020		T30	7808
valid_sources[0x77]	1310600	1			T1	1550		T2	2190		T30	7826
valid_sources[0x78]	1315026	1			T1	1625		T2	2202		T30	7936
valid_sources[0x79]	1340212	1			T1	1576		T2	2088		T30	7956
valid_sources[0x7a]	1332194	1			T1	1616		T2	2901		T30	7887
valid_sources[0x7b]	1312133	1			T1	1547		T2	1881		T30	7830
valid_sources[0x7c]	2611192	1			T1	1548		T2	2911		T30	7796
valid_sources[0x7d]	1310863	1			T1	1671		T2	2941		T30	7852
valid_sources[0x7e]	1309974	1			T1	1515		T2	2523		T30	7958
valid_sources[0x7f]	1305462	1			T1	1577		T2	2823		T15	1930
valid_sources[0x80]	2176080	1			T1	1548		T2	2760		T30	7777

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

72548417

1

T1

67692

T2

122244

T3

2

values[0x0]

all_enables

biggest_size

61806780

1

T1

136716

T2

99328

T3

35

values[0x1]

all_enables

biggest_size

53305079

1

T1

136833

T2

88636

T3

20