Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

266768136

1

T1

64287

T2

313713

T3

23

full_word

187957555

1

T1

341241

T2

310208

T3

57

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	454725381	1			T1	405528		T2	623921		T3	80
auto[TlIntgErrCmd]	96	1			T120	6		T121	5		T122	6
auto[TlIntgErrData]	101	1			T120	2		T121	3		T122	8
auto[TlIntgErrBoth]	113	1			T120	2		T121	2		T122	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

233887448

1

T1

128048

T2

317204

T3

21

auto[1]

220838243

1

T1

277480

T2

306717

T3

59

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	161264178	1			T1	60356		T2	194960		T3	19
auto[TlIntgErrNone]	partial	auto[1]	105503673	1			T1	3931		T2	118753		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	72623133	1			T1	67692		T2	122244		T3	2
auto[TlIntgErrNone]	full_word	auto[1]	115334397	1			T1	273549		T2	187964		T3	55
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T120	4		T121	2		T122	2
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T120	1		T121	2		T122	4
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T121	1		T181	1		T180	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T120	1		T184	1		T185	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T120	1		T121	2		T122	3
auto[TlIntgErrData]	partial	auto[1]	46	1			T120	1		T122	5		T186	4
auto[TlIntgErrData]	full_word	auto[0]	2	1			T121	1		T187	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1			T180	1		T184	1		T188	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T120	1		T121	1		T122	3
auto[TlIntgErrBoth]	partial	auto[1]	63	1			T120	1		T121	1		T122	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T186	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T181	1		T187	1		T189	1