Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1115000	0	0
entropy_period_rd_A	2147483647	1699	0	0
intr_enable_rd_A	2147483647	2326	0	0
prefix_0_rd_A	2147483647	1582	0	0
prefix_10_rd_A	2147483647	1565	0	0
prefix_1_rd_A	2147483647	1564	0	0
prefix_2_rd_A	2147483647	1722	0	0
prefix_3_rd_A	2147483647	1657	0	0
prefix_4_rd_A	2147483647	1591	0	0
prefix_5_rd_A	2147483647	1648	0	0
prefix_6_rd_A	2147483647	1489	0	0
prefix_7_rd_A	2147483647	1470	0	0
prefix_8_rd_A	2147483647	1468	0	0
prefix_9_rd_A	2147483647	1621	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1115000	0	0
T14	594984	85553	0	0
T21	0	155727	0	0
T23	80011	0	0	0
T51	0	53511	0	0
T107	53841	0	0	0
T108	133672	0	0	0
T126	0	118234	0	0
T127	0	118381	0	0
T128	0	26121	0	0
T129	0	36185	0	0
T130	0	56917	0	0
T131	0	48920	0	0
T132	0	28005	0	0
T133	3262	0	0	0
T134	152010	0	0	0
T135	351231	0	0	0
T136	890031	0	0	0
T137	493205	0	0	0
T138	926948	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1699	0	0
T71	235659	33	0	0
T72	0	100	0	0
T81	0	40	0	0
T85	0	39	0	0
T119	0	74	0	0
T148	0	12	0	0
T149	0	4	0	0
T150	0	32	0	0
T151	0	18	0	0
T152	0	16	0	0
T153	705401	0	0	0
T154	189734	0	0	0
T155	231212	0	0	0
T156	13425	0	0	0
T157	457159	0	0	0
T158	150558	0	0	0
T159	195763	0	0	0
T160	506424	0	0	0
T161	338589	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2326	0	0
T71	235659	63	0	0
T72	0	60	0	0
T85	0	53	0	0
T148	0	11	0	0
T149	0	5	0	0
T150	0	14	0	0
T151	0	21	0	0
T153	705401	0	0	0
T154	189734	0	0	0
T155	231212	0	0	0
T156	13425	0	0	0
T157	457159	0	0	0
T158	150558	0	0	0
T159	195763	0	0	0
T160	506424	0	0	0
T161	338589	0	0	0
T162	0	17	0	0
T163	0	18	0	0
T164	0	9	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1582	0	0
T71	235659	65	0	0
T72	0	87	0	0
T81	0	24	0	0
T85	0	30	0	0
T119	0	42	0	0
T148	0	9	0	0
T149	0	7	0	0
T150	0	25	0	0
T151	0	53	0	0
T152	0	5	0	0
T153	705401	0	0	0
T154	189734	0	0	0
T155	231212	0	0	0
T156	13425	0	0	0
T157	457159	0	0	0
T158	150558	0	0	0
T159	195763	0	0	0
T160	506424	0	0	0
T161	338589	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1565	0	0
T71	235659	37	0	0
T72	0	54	0	0
T81	0	23	0	0
T85	0	25	0	0
T119	0	47	0	0
T148	0	12	0	0
T150	0	8	0	0
T151	0	51	0	0
T152	0	2	0	0
T153	705401	0	0	0
T154	189734	0	0	0
T155	231212	0	0	0
T156	13425	0	0	0
T157	457159	0	0	0
T158	150558	0	0	0
T159	195763	0	0	0
T160	506424	0	0	0
T161	338589	0	0	0
T165	0	10	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1564	0	0
T71	235659	73	0	0
T72	0	71	0	0
T81	0	24	0	0
T85	0	31	0	0
T119	0	59	0	0
T148	0	21	0	0
T149	0	3	0	0
T150	0	23	0	0
T151	0	34	0	0
T153	705401	0	0	0
T154	189734	0	0	0
T155	231212	0	0	0
T156	13425	0	0	0
T157	457159	0	0	0
T158	150558	0	0	0
T159	195763	0	0	0
T160	506424	0	0	0
T161	338589	0	0	0
T165	0	10	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1722	0	0
T71	235659	57	0	0
T72	0	54	0	0
T85	0	31	0	0
T119	0	66	0	0
T148	0	20	0	0
T149	0	4	0	0
T150	0	23	0	0
T151	0	96	0	0
T153	705401	0	0	0
T154	189734	0	0	0
T155	231212	0	0	0
T156	13425	0	0	0
T157	457159	0	0	0
T158	150558	0	0	0
T159	195763	0	0	0
T160	506424	0	0	0
T161	338589	0	0	0
T166	0	6	0	0
T167	0	3	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1657	0	0
T71	235659	78	0	0
T72	0	65	0	0
T81	0	22	0	0
T85	0	39	0	0
T119	0	59	0	0
T148	0	16	0	0
T149	0	8	0	0
T150	0	24	0	0
T151	0	62	0	0
T153	705401	0	0	0
T154	189734	0	0	0
T155	231212	0	0	0
T156	13425	0	0	0
T157	457159	0	0	0
T158	150558	0	0	0
T159	195763	0	0	0
T160	506424	0	0	0
T161	338589	0	0	0
T168	0	1	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1591	0	0
T71	235659	66	0	0
T72	0	76	0	0
T81	0	33	0	0
T82	0	26	0	0
T85	0	40	0	0
T119	0	56	0	0
T148	0	12	0	0
T149	0	2	0	0
T150	0	14	0	0
T153	705401	0	0	0
T154	189734	0	0	0
T155	231212	0	0	0
T156	13425	0	0	0
T157	457159	0	0	0
T158	150558	0	0	0
T159	195763	0	0	0
T160	506424	0	0	0
T161	338589	0	0	0
T165	0	12	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1648	0	0
T71	235659	66	0	0
T72	0	74	0	0
T81	0	32	0	0
T82	0	9	0	0
T85	0	27	0	0
T119	0	49	0	0
T148	0	18	0	0
T150	0	13	0	0
T151	0	25	0	0
T153	705401	0	0	0
T154	189734	0	0	0
T155	231212	0	0	0
T156	13425	0	0	0
T157	457159	0	0	0
T158	150558	0	0	0
T159	195763	0	0	0
T160	506424	0	0	0
T161	338589	0	0	0
T165	0	3	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1489	0	0
T71	235659	49	0	0
T72	0	96	0	0
T81	0	26	0	0
T85	0	20	0	0
T119	0	56	0	0
T148	0	13	0	0
T150	0	10	0	0
T151	0	15	0	0
T152	0	2	0	0
T153	705401	0	0	0
T154	189734	0	0	0
T155	231212	0	0	0
T156	13425	0	0	0
T157	457159	0	0	0
T158	150558	0	0	0
T159	195763	0	0	0
T160	506424	0	0	0
T161	338589	0	0	0
T168	0	2	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1470	0	0
T71	235659	63	0	0
T72	0	96	0	0
T81	0	19	0	0
T85	0	26	0	0
T119	0	48	0	0
T148	0	17	0	0
T149	0	5	0	0
T150	0	30	0	0
T151	0	19	0	0
T153	705401	0	0	0
T154	189734	0	0	0
T155	231212	0	0	0
T156	13425	0	0	0
T157	457159	0	0	0
T158	150558	0	0	0
T159	195763	0	0	0
T160	506424	0	0	0
T161	338589	0	0	0
T168	0	7	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1468	0	0
T71	235659	57	0	0
T72	0	59	0	0
T81	0	17	0	0
T85	0	46	0	0
T119	0	49	0	0
T148	0	16	0	0
T149	0	7	0	0
T150	0	18	0	0
T151	0	17	0	0
T153	705401	0	0	0
T154	189734	0	0	0
T155	231212	0	0	0
T156	13425	0	0	0
T157	457159	0	0	0
T158	150558	0	0	0
T159	195763	0	0	0
T160	506424	0	0	0
T161	338589	0	0	0
T168	0	3	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1621	0	0
T71	235659	52	0	0
T72	0	51	0	0
T81	0	20	0	0
T85	0	20	0	0
T119	0	40	0	0
T148	0	11	0	0
T149	0	6	0	0
T150	0	30	0	0
T151	0	36	0	0
T153	705401	0	0	0
T154	189734	0	0	0
T155	231212	0	0	0
T156	13425	0	0	0
T157	457159	0	0	0
T158	150558	0	0	0
T159	195763	0	0	0
T160	506424	0	0	0
T161	338589	0	0	0
T168	0	4	0	0