Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	256793103	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

184345688

1

T1

11

T2

175194

T3

344931

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	228028645	1			T1	1		T2	236263		T3	455387
values[0x0]	102379415	1			T1	20		T2	109145		T3	217948
values[0x1]	110730731	1			T1	15		T2	121383		T3	237713

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	199578483	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

241560308

1

T1

14

T2

240435

T3

469688

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1251662	1			T2	1879		T3	3508		T4	4
valid_sources[0x01]	1245077	1			T2	1786		T3	3444		T4	13
valid_sources[0x02]	1340246	1			T2	1823		T3	3577		T4	14
valid_sources[0x03]	1250479	1			T2	1944		T3	3512		T4	9
valid_sources[0x04]	1320619	1			T2	1781		T3	3802		T4	12
valid_sources[0x05]	1626316	1			T2	1750		T3	3451		T4	10
valid_sources[0x06]	2124784	1			T2	1823		T3	3259		T4	2
valid_sources[0x07]	1250580	1			T2	1768		T3	3448		T4	7
valid_sources[0x08]	2108982	1			T2	2024		T3	3608		T4	11
valid_sources[0x09]	1242525	1			T2	1865		T3	3558		T4	10
valid_sources[0x0a]	1313421	1			T2	2006		T3	3430		T4	1
valid_sources[0x0b]	1241824	1			T2	1945		T3	3644		T4	8
valid_sources[0x0c]	1383101	1			T2	1870		T3	3408		T4	5
valid_sources[0x0d]	1249079	1			T2	1833		T3	3760		T4	4
valid_sources[0x0e]	1250191	1			T2	1824		T3	3529		T4	11
valid_sources[0x0f]	1243648	1			T2	1763		T3	3473		T4	5
valid_sources[0x10]	1249089	1			T2	1896		T3	3484		T4	3
valid_sources[0x11]	1246271	1			T2	1740		T3	3621		T4	2
valid_sources[0x12]	1446765	1			T2	1771		T3	3697		T4	5
valid_sources[0x13]	4508329	1			T2	1838		T3	3752		T4	5
valid_sources[0x14]	4062091	1			T2	1866		T3	3779		T4	4
valid_sources[0x15]	1240071	1			T2	1858		T3	3487		T4	3
valid_sources[0x16]	1248808	1			T2	1829		T3	3619		T4	6
valid_sources[0x17]	1292425	1			T2	1807		T3	3562		T4	5
valid_sources[0x18]	1330951	1			T2	1803		T3	3441		T4	3
valid_sources[0x19]	1267429	1			T2	1595		T3	3717		T4	6
valid_sources[0x1a]	1244185	1			T2	1809		T3	3708		T4	3
valid_sources[0x1b]	1245787	1			T2	1783		T3	3510		T4	2
valid_sources[0x1c]	1248195	1			T2	1840		T3	3773		T4	12
valid_sources[0x1d]	2147219	1			T2	1895		T3	3570		T4	5
valid_sources[0x1e]	1896204	1			T2	1788		T3	3482		T4	7
valid_sources[0x1f]	1707571	1			T2	1893		T3	3343		T4	7
valid_sources[0x20]	1244460	1			T2	1829		T3	3317		T4	6
valid_sources[0x21]	1247674	1			T2	1861		T3	3378		T4	12
valid_sources[0x22]	3559560	1			T2	1782		T3	3643		T4	8
valid_sources[0x23]	2097203	1			T2	1835		T3	3672		T4	7
valid_sources[0x24]	2108464	1			T2	1728		T3	3566		T4	8
valid_sources[0x25]	3210447	1			T2	1979		T3	3596		T4	2
valid_sources[0x26]	1245105	1			T2	1972		T3	3505		T4	1
valid_sources[0x27]	1238793	1			T2	1760		T3	3635		T4	2
valid_sources[0x28]	2591925	1			T2	1930		T3	3449		T4	10
valid_sources[0x29]	1248136	1			T2	1785		T3	3365		T4	14
valid_sources[0x2a]	1400037	1			T2	1961		T3	3379		T4	7
valid_sources[0x2b]	1252730	1			T2	1804		T3	3366		T4	7
valid_sources[0x2c]	1250168	1			T2	1863		T3	3366		T4	3
valid_sources[0x2d]	3201404	1			T2	1916		T3	3600		T4	7
valid_sources[0x2e]	1246314	1			T2	1905		T3	3443		T4	11
valid_sources[0x2f]	1509474	1			T2	1785		T3	3623		T4	12
valid_sources[0x30]	1250335	1			T2	1891		T3	3532		T4	8
valid_sources[0x31]	3581264	1			T2	1854		T3	3925		T4	7
valid_sources[0x32]	1250039	1			T2	1800		T3	3340		T4	2
valid_sources[0x33]	1252825	1			T2	1959		T3	3557		T18	7680
valid_sources[0x34]	1250248	1			T2	1653		T3	3633		T4	1
valid_sources[0x35]	2081923	1			T2	1789		T3	3688		T4	6
valid_sources[0x36]	1257000	1			T2	1829		T3	3502		T4	2
valid_sources[0x37]	3618540	1			T2	1832		T3	3567		T4	2
valid_sources[0x38]	1248438	1			T2	1870		T3	3557		T4	4
valid_sources[0x39]	1248358	1			T2	1735		T3	3379		T4	14
valid_sources[0x3a]	2088541	1			T2	1673		T3	3413		T4	5
valid_sources[0x3b]	2114254	1			T2	1846		T3	3712		T4	5
valid_sources[0x3c]	1270177	1			T2	1940		T3	3626		T4	1
valid_sources[0x3d]	1316547	1			T2	1696		T3	3520		T4	1
valid_sources[0x3e]	1253441	1			T2	1682		T3	3398		T4	6
valid_sources[0x3f]	2268308	1			T2	1540		T3	3512		T4	15
valid_sources[0x40]	1294549	1			T2	1888		T3	3556		T4	1
valid_sources[0x41]	1315182	1			T2	2031		T3	3466		T4	1
valid_sources[0x42]	1249297	1			T2	1908		T3	3474		T4	6
valid_sources[0x43]	1444974	1			T2	1998		T3	3570		T4	4
valid_sources[0x44]	2267412	1			T2	1630		T3	3591		T4	7
valid_sources[0x45]	1244540	1			T2	1771		T3	3550		T4	7
valid_sources[0x46]	1246371	1			T2	1927		T3	3773		T4	7
valid_sources[0x47]	1245387	1			T2	1886		T3	3469		T4	6
valid_sources[0x48]	1243198	1			T1	36		T2	1795		T3	3450
valid_sources[0x49]	1250868	1			T2	1905		T3	3441		T4	1
valid_sources[0x4a]	5689215	1			T2	1881		T3	3420		T4	4
valid_sources[0x4b]	1247845	1			T2	1987		T3	3421		T4	18
valid_sources[0x4c]	1242371	1			T2	1695		T3	3767		T4	14
valid_sources[0x4d]	1275343	1			T2	1801		T3	3688		T4	18
valid_sources[0x4e]	1242415	1			T2	1849		T3	3417		T4	10
valid_sources[0x4f]	1789410	1			T2	1757		T3	3485		T4	4
valid_sources[0x50]	5579748	1			T2	1777		T3	3367		T4	6
valid_sources[0x51]	3579323	1			T2	1900		T3	3766		T4	4
valid_sources[0x52]	2149802	1			T2	1839		T3	3594		T4	10
valid_sources[0x53]	1247063	1			T2	1819		T3	3515		T4	7
valid_sources[0x54]	1247899	1			T2	1631		T3	3264		T4	3
valid_sources[0x55]	1248231	1			T2	2016		T3	3801		T4	6
valid_sources[0x56]	1250266	1			T2	1661		T3	3673		T4	5
valid_sources[0x57]	1253773	1			T2	1871		T3	3764		T4	10
valid_sources[0x58]	1255383	1			T2	1712		T3	3819		T4	10
valid_sources[0x59]	1435349	1			T2	1982		T3	3549		T4	16
valid_sources[0x5a]	1247409	1			T2	1986		T3	3544		T4	1
valid_sources[0x5b]	1247989	1			T2	1669		T3	3513		T4	3
valid_sources[0x5c]	1248857	1			T2	1815		T3	3554		T4	10
valid_sources[0x5d]	1357290	1			T2	1864		T3	3784		T4	7
valid_sources[0x5e]	4946886	1			T2	1889		T3	3728		T4	3
valid_sources[0x5f]	1249886	1			T2	1966		T3	3582		T4	4
valid_sources[0x60]	1258520	1			T2	1810		T3	3761		T4	4
valid_sources[0x61]	1254416	1			T2	1778		T3	3579		T4	7
valid_sources[0x62]	1348219	1			T2	1888		T3	3560		T4	3
valid_sources[0x63]	3218146	1			T2	1858		T3	3253		T4	4
valid_sources[0x64]	1705954	1			T2	1791		T3	3495		T4	7
valid_sources[0x65]	1252588	1			T2	1769		T3	3479		T4	5
valid_sources[0x66]	1244916	1			T2	1925		T3	3476		T4	7
valid_sources[0x67]	3573117	1			T2	1747		T3	3744		T4	6
valid_sources[0x68]	1241177	1			T2	1734		T3	3558		T4	1
valid_sources[0x69]	1252723	1			T2	1957		T3	3571		T4	10
valid_sources[0x6a]	3253983	1			T2	1738		T3	3679		T4	8
valid_sources[0x6b]	1252901	1			T2	1918		T3	3539		T4	11
valid_sources[0x6c]	1250555	1			T2	1796		T3	3377		T4	1
valid_sources[0x6d]	1346159	1			T2	1697		T3	3485		T4	5
valid_sources[0x6e]	1384337	1			T2	1741		T3	3734		T4	1
valid_sources[0x6f]	1242951	1			T2	1889		T3	3449		T4	1
valid_sources[0x70]	1353611	1			T2	1802		T3	3627		T4	7
valid_sources[0x71]	1698271	1			T2	1670		T3	3899		T4	10
valid_sources[0x72]	1248424	1			T2	1835		T3	3628		T4	11
valid_sources[0x73]	1251237	1			T2	1892		T3	3573		T18	7693
valid_sources[0x74]	1248728	1			T2	1759		T3	3596		T4	6
valid_sources[0x75]	1253670	1			T2	1740		T3	3478		T4	8
valid_sources[0x76]	1247441	1			T2	1720		T3	3443		T4	7
valid_sources[0x77]	3588241	1			T2	1918		T3	3638		T4	11
valid_sources[0x78]	1244222	1			T2	1958		T3	3612		T4	1
valid_sources[0x79]	1245144	1			T2	1827		T3	3636		T4	3
valid_sources[0x7a]	1262263	1			T2	1839		T3	3434		T4	2
valid_sources[0x7b]	1251187	1			T2	1890		T3	3515		T4	9
valid_sources[0x7c]	1257959	1			T2	1862		T3	3655		T4	3
valid_sources[0x7d]	1910846	1			T2	1837		T3	3236		T4	2
valid_sources[0x7e]	1350363	1			T2	1840		T3	3624		T4	12
valid_sources[0x7f]	1707476	1			T2	1964		T3	3625		T18	7830
valid_sources[0x80]	1655501	1			T2	1776		T3	3611		T4	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

71471836

1

T1

1

T2

64973

T3

118138

values[0x0]

all_enables

biggest_size

60633096

1

T1

8

T2

59559

T3

122943

values[0x1]

all_enables

biggest_size

52240756

1

T1

2

T2

50662

T3

103850