Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

259867922

1

T1

25

T2

291597

T3

566117

full_word

184538057

1

T1

11

T2

175194

T3

344931

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	444405699	1			T1	36		T2	466791		T3	911048
auto[TlIntgErrCmd]	110	1			T115	11		T116	3		T117	8
auto[TlIntgErrData]	93	1			T115	6		T116	8		T117	6
auto[TlIntgErrBoth]	77	1			T115	3		T116	9		T117	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

228630743

1

T1

1

T2

236263

T3

455387

auto[1]

215775236

1

T1

35

T2

230528

T3

455661

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	157109779	1			T2	171290		T3	337249		T4	888
auto[TlIntgErrNone]	partial	auto[1]	102757887	1			T1	25		T2	120307		T3	228868
auto[TlIntgErrNone]	full_word	auto[0]	71520848	1			T1	1		T2	64973		T3	118138
auto[TlIntgErrNone]	full_word	auto[1]	113017185	1			T1	10		T2	110221		T3	226793
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T115	2		T116	1		T117	3
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T115	8		T116	2		T117	4
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T115	1		T147	1		T170	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T117	1		T147	1		T171	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T115	2		T116	3		T117	3
auto[TlIntgErrData]	partial	auto[1]	42	1			T115	3		T116	5		T117	2
auto[TlIntgErrData]	full_word	auto[0]	1	1			T172	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1			T115	1		T117	1		T173	2
auto[TlIntgErrBoth]	partial	auto[0]	27	1			T115	2		T116	2		T147	1
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T115	1		T116	6		T117	5
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T116	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T117	1		T174	1		T175	1