Module Definition
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Module : kmac_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.kmac_csr_assert 100.00 100.00


Module Instance : tb.dut.kmac_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.76 98.75 96.74 100.00 100.00 97.06 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : kmac_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 14 14 100.00 14 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 14 14 100.00 14 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 2147483647 714934 0 0
entropy_period_rd_A 2147483647 1718 0 0
intr_enable_rd_A 2147483647 2385 0 0
prefix_0_rd_A 2147483647 1488 0 0
prefix_10_rd_A 2147483647 1497 0 0
prefix_1_rd_A 2147483647 1472 0 0
prefix_2_rd_A 2147483647 1488 0 0
prefix_3_rd_A 2147483647 1384 0 0
prefix_4_rd_A 2147483647 1469 0 0
prefix_5_rd_A 2147483647 1416 0 0
prefix_6_rd_A 2147483647 1487 0 0
prefix_7_rd_A 2147483647 1545 0 0
prefix_8_rd_A 2147483647 1506 0 0
prefix_9_rd_A 2147483647 1455 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 714934 0 0
T31 3250 0 0 0
T47 668783 56273 0 0
T48 0 159455 0 0
T49 0 27010 0 0
T88 0 16811 0 0
T89 0 44115 0 0
T121 0 19931 0 0
T122 0 12074 0 0
T123 0 84382 0 0
T124 0 147445 0 0
T125 0 34397 0 0
T126 25095 0 0 0
T127 437212 0 0 0
T128 392761 0 0 0
T129 445843 0 0 0
T130 620230 0 0 0
T131 19401 0 0 0
T132 94590 0 0 0
T133 121115 0 0 0

entropy_period_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1718 0 0
T88 185680 27 0 0
T89 0 105 0 0
T99 0 25 0 0
T115 0 110 0 0
T142 0 6 0 0
T143 0 7 0 0
T144 0 18 0 0
T145 0 7 0 0
T146 0 14 0 0
T147 0 36 0 0
T148 174809 0 0 0
T149 152357 0 0 0
T150 4580 0 0 0
T151 158783 0 0 0
T152 395704 0 0 0
T153 955374 0 0 0
T154 85231 0 0 0
T155 292636 0 0 0
T156 690290 0 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2385 0 0
T88 185680 29 0 0
T89 0 130 0 0
T99 0 25 0 0
T115 0 188 0 0
T118 0 13 0 0
T143 0 10 0 0
T144 0 46 0 0
T145 0 57 0 0
T146 0 19 0 0
T147 0 39 0 0
T148 174809 0 0 0
T149 152357 0 0 0
T150 4580 0 0 0
T151 158783 0 0 0
T152 395704 0 0 0
T153 955374 0 0 0
T154 85231 0 0 0
T155 292636 0 0 0
T156 690290 0 0 0

prefix_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1488 0 0
T88 185680 14 0 0
T89 0 123 0 0
T99 0 8 0 0
T115 0 87 0 0
T143 0 26 0 0
T144 0 8 0 0
T145 0 8 0 0
T146 0 19 0 0
T147 0 6 0 0
T148 174809 0 0 0
T149 152357 0 0 0
T150 4580 0 0 0
T151 158783 0 0 0
T152 395704 0 0 0
T153 955374 0 0 0
T154 85231 0 0 0
T155 292636 0 0 0
T156 690290 0 0 0
T157 0 26 0 0

prefix_10_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1497 0 0
T88 185680 21 0 0
T89 0 90 0 0
T99 0 24 0 0
T115 0 77 0 0
T143 0 2 0 0
T144 0 47 0 0
T145 0 23 0 0
T146 0 14 0 0
T147 0 25 0 0
T148 174809 0 0 0
T149 152357 0 0 0
T150 4580 0 0 0
T151 158783 0 0 0
T152 395704 0 0 0
T153 955374 0 0 0
T154 85231 0 0 0
T155 292636 0 0 0
T156 690290 0 0 0
T157 0 17 0 0

prefix_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1472 0 0
T88 185680 20 0 0
T89 0 118 0 0
T99 0 25 0 0
T115 0 79 0 0
T143 0 11 0 0
T144 0 25 0 0
T145 0 13 0 0
T146 0 16 0 0
T147 0 23 0 0
T148 174809 0 0 0
T149 152357 0 0 0
T150 4580 0 0 0
T151 158783 0 0 0
T152 395704 0 0 0
T153 955374 0 0 0
T154 85231 0 0 0
T155 292636 0 0 0
T156 690290 0 0 0
T157 0 40 0 0

prefix_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1488 0 0
T88 185680 13 0 0
T89 0 170 0 0
T99 0 9 0 0
T115 0 65 0 0
T143 0 8 0 0
T144 0 32 0 0
T145 0 25 0 0
T146 0 15 0 0
T147 0 21 0 0
T148 174809 0 0 0
T149 152357 0 0 0
T150 4580 0 0 0
T151 158783 0 0 0
T152 395704 0 0 0
T153 955374 0 0 0
T154 85231 0 0 0
T155 292636 0 0 0
T156 690290 0 0 0
T157 0 15 0 0

prefix_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1384 0 0
T88 185680 15 0 0
T89 0 86 0 0
T99 0 22 0 0
T115 0 72 0 0
T143 0 4 0 0
T144 0 24 0 0
T145 0 17 0 0
T146 0 27 0 0
T147 0 13 0 0
T148 174809 0 0 0
T149 152357 0 0 0
T150 4580 0 0 0
T151 158783 0 0 0
T152 395704 0 0 0
T153 955374 0 0 0
T154 85231 0 0 0
T155 292636 0 0 0
T156 690290 0 0 0
T157 0 31 0 0

prefix_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1469 0 0
T88 185680 13 0 0
T89 0 104 0 0
T99 0 25 0 0
T115 0 86 0 0
T143 0 14 0 0
T144 0 28 0 0
T145 0 9 0 0
T146 0 9 0 0
T147 0 20 0 0
T148 174809 0 0 0
T149 152357 0 0 0
T150 4580 0 0 0
T151 158783 0 0 0
T152 395704 0 0 0
T153 955374 0 0 0
T154 85231 0 0 0
T155 292636 0 0 0
T156 690290 0 0 0
T157 0 22 0 0

prefix_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1416 0 0
T88 185680 27 0 0
T89 0 92 0 0
T99 0 20 0 0
T115 0 75 0 0
T143 0 15 0 0
T144 0 17 0 0
T145 0 35 0 0
T146 0 13 0 0
T147 0 18 0 0
T148 174809 0 0 0
T149 152357 0 0 0
T150 4580 0 0 0
T151 158783 0 0 0
T152 395704 0 0 0
T153 955374 0 0 0
T154 85231 0 0 0
T155 292636 0 0 0
T156 690290 0 0 0
T157 0 19 0 0

prefix_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1487 0 0
T88 185680 29 0 0
T89 0 85 0 0
T99 0 8 0 0
T115 0 89 0 0
T143 0 6 0 0
T144 0 4 0 0
T145 0 5 0 0
T146 0 21 0 0
T147 0 13 0 0
T148 174809 0 0 0
T149 152357 0 0 0
T150 4580 0 0 0
T151 158783 0 0 0
T152 395704 0 0 0
T153 955374 0 0 0
T154 85231 0 0 0
T155 292636 0 0 0
T156 690290 0 0 0
T157 0 18 0 0

prefix_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1545 0 0
T88 185680 50 0 0
T89 0 130 0 0
T99 0 12 0 0
T115 0 74 0 0
T143 0 10 0 0
T144 0 12 0 0
T145 0 23 0 0
T146 0 11 0 0
T147 0 34 0 0
T148 174809 0 0 0
T149 152357 0 0 0
T150 4580 0 0 0
T151 158783 0 0 0
T152 395704 0 0 0
T153 955374 0 0 0
T154 85231 0 0 0
T155 292636 0 0 0
T156 690290 0 0 0
T157 0 23 0 0

prefix_8_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1506 0 0
T88 185680 31 0 0
T89 0 107 0 0
T99 0 11 0 0
T115 0 84 0 0
T143 0 6 0 0
T144 0 1 0 0
T145 0 53 0 0
T146 0 27 0 0
T147 0 10 0 0
T148 174809 0 0 0
T149 152357 0 0 0
T150 4580 0 0 0
T151 158783 0 0 0
T152 395704 0 0 0
T153 955374 0 0 0
T154 85231 0 0 0
T155 292636 0 0 0
T156 690290 0 0 0
T157 0 31 0 0

prefix_9_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1455 0 0
T88 185680 36 0 0
T89 0 143 0 0
T99 0 31 0 0
T115 0 93 0 0
T143 0 12 0 0
T144 0 4 0 0
T145 0 32 0 0
T146 0 18 0 0
T147 0 22 0 0
T148 174809 0 0 0
T149 152357 0 0 0
T150 4580 0 0 0
T151 158783 0 0 0
T152 395704 0 0 0
T153 955374 0 0 0
T154 85231 0 0 0
T155 292636 0 0 0
T156 690290 0 0 0
T157 0 11 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%